HMAC Simulation Results

Monday September 01 2025 16:38:37 UTC

GitHub Revision: 9bb489f

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 7.690s 445.349us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 0.810s 17.170us 1 1 100.00
V1 csr_rw hmac_csr_rw 0.820s 36.334us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 3.770s 2.129ms 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 4.670s 376.464us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 1.010s 34.451us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 0.820s 36.334us 1 1 100.00
hmac_csr_aliasing 4.670s 376.464us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 2.840s 108.868us 1 1 100.00
V2 back_pressure hmac_back_pressure 53.470s 1.290ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 8.120s 186.772us 1 1 100.00
hmac_test_sha384_vectors 20.180s 237.895us 1 1 100.00
hmac_test_sha512_vectors 8.164m 31.891ms 1 1 100.00
hmac_test_hmac256_vectors 9.240s 566.873us 1 1 100.00
hmac_test_hmac384_vectors 9.330s 342.547us 1 1 100.00
hmac_test_hmac512_vectors 10.250s 865.347us 1 1 100.00
V2 burst_wr hmac_burst_wr 21.670s 7.281ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 1.300m 576.738us 1 1 100.00
V2 error hmac_error 25.430s 6.003ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 16.680s 462.047us 1 1 100.00
V2 save_and_restore hmac_smoke 7.690s 445.349us 1 1 100.00
hmac_long_msg 2.840s 108.868us 1 1 100.00
hmac_back_pressure 53.470s 1.290ms 1 1 100.00
hmac_datapath_stress 1.300m 576.738us 1 1 100.00
hmac_burst_wr 21.670s 7.281ms 1 1 100.00
hmac_stress_all 23.190s 20.117ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 7.690s 445.349us 1 1 100.00
hmac_long_msg 2.840s 108.868us 1 1 100.00
hmac_back_pressure 53.470s 1.290ms 1 1 100.00
hmac_datapath_stress 1.300m 576.738us 1 1 100.00
hmac_wipe_secret 16.680s 462.047us 1 1 100.00
hmac_test_sha256_vectors 8.120s 186.772us 1 1 100.00
hmac_test_sha384_vectors 20.180s 237.895us 1 1 100.00
hmac_test_sha512_vectors 8.164m 31.891ms 1 1 100.00
hmac_test_hmac256_vectors 9.240s 566.873us 1 1 100.00
hmac_test_hmac384_vectors 9.330s 342.547us 1 1 100.00
hmac_test_hmac512_vectors 10.250s 865.347us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 7.690s 445.349us 1 1 100.00
hmac_long_msg 2.840s 108.868us 1 1 100.00
hmac_back_pressure 53.470s 1.290ms 1 1 100.00
hmac_datapath_stress 1.300m 576.738us 1 1 100.00
hmac_burst_wr 21.670s 7.281ms 1 1 100.00
hmac_error 25.430s 6.003ms 1 1 100.00
hmac_wipe_secret 16.680s 462.047us 1 1 100.00
hmac_test_sha256_vectors 8.120s 186.772us 1 1 100.00
hmac_test_sha384_vectors 20.180s 237.895us 1 1 100.00
hmac_test_sha512_vectors 8.164m 31.891ms 1 1 100.00
hmac_test_hmac256_vectors 9.240s 566.873us 1 1 100.00
hmac_test_hmac384_vectors 9.330s 342.547us 1 1 100.00
hmac_test_hmac512_vectors 10.250s 865.347us 1 1 100.00
hmac_stress_all 23.190s 20.117ms 1 1 100.00
V2 stress_all hmac_stress_all 23.190s 20.117ms 1 1 100.00
V2 alert_test hmac_alert_test 0.730s 144.301us 1 1 100.00
V2 intr_test hmac_intr_test 0.700s 46.286us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.780s 357.447us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.780s 357.447us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 0.810s 17.170us 1 1 100.00
hmac_csr_rw 0.820s 36.334us 1 1 100.00
hmac_csr_aliasing 4.670s 376.464us 1 1 100.00
hmac_same_csr_outstanding 2.550s 229.239us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 0.810s 17.170us 1 1 100.00
hmac_csr_rw 0.820s 36.334us 1 1 100.00
hmac_csr_aliasing 4.670s 376.464us 1 1 100.00
hmac_same_csr_outstanding 2.550s 229.239us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.040s 254.368us 1 1 100.00
hmac_tl_intg_err 3.580s 1.351ms 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 3.580s 1.351ms 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 7.690s 445.349us 1 1 100.00
V3 stress_reset hmac_stress_reset 0.880s 85.582us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 2.033m 13.162ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 2.590s 110.274us 1 1 100.00
TOTAL 28 28 100.00