I2C Simulation Results

Monday September 01 2025 16:38:37 UTC

GitHub Revision: 9bb489f

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	12.880s	1.408ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	8.540s	4.016ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.680s	19.843us	1	1	100.00
V1	csr_rw	i2c_csr_rw	0.700s	26.182us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	2.030s	547.308us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	0.990s	244.190us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	0.780s	120.966us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.700s	26.182us	1	1	100.00
		i2c_csr_aliasing	0.990s	244.190us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	0.680s	20.713us	0	1	0.00
V2	host_stress_all	i2c_host_stress_all	33.120s	1.163ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	4.441m	72.462ms	1	1	100.00
V2	host_override	i2c_host_override	0.580s	26.607us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	1.612m	5.346ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	39.650s	9.555ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	0.880s	472.753us	1	1	100.00
		i2c_host_fifo_fmt_empty	5.990s	415.305us	1	1	100.00
		i2c_host_fifo_reset_rx	4.860s	290.518us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	1.191m	15.150ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	12.130s	2.390ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	3.950s	302.939us	1	1	100.00
V2	target_glitch	i2c_target_glitch	1.960s	1.124ms	0	1	0.00
V2	target_stress_all	i2c_target_stress_all	7.055m	29.902ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	2.600s	544.966us	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	26.910s	4.004ms	1	1	100.00
		i2c_target_intr_smoke	5.600s	3.271ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.190s	252.005us	1	1	100.00
		i2c_target_fifo_reset_tx	0.800s	436.207us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	27.470s	35.863ms	1	1	100.00
		i2c_target_stress_rd	26.910s	4.004ms	1	1	100.00
		i2c_target_intr_stress_wr	2.626m	16.560ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	4.890s	5.735ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	35.650s	5.009ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	2.710s	716.933us	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	1.350s	221.052us	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	1.920s	667.235us	1	1	100.00
		i2c_target_fifo_watermarks_tx	0.920s	537.602us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	4.441m	72.462ms	1	1	100.00
		i2c_host_perf_precise	1.210s	73.521us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	12.130s	2.390ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	2.660s	173.480us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	1.860s	1.048ms	1	1	100.00
		i2c_target_nack_acqfull_addr	1.670s	2.042ms	1	1	100.00
		i2c_target_nack_txstretch	0.970s	284.925us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	3.790s	384.919us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	1.420s	394.435us	1	1	100.00
V2	alert_test	i2c_alert_test	0.670s	23.435us	1	1	100.00
V2	intr_test	i2c_intr_test	0.610s	38.728us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	1.180s	461.395us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	1.180s	461.395us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.680s	19.843us	1	1	100.00
		i2c_csr_rw	0.700s	26.182us	1	1	100.00
		i2c_csr_aliasing	0.990s	244.190us	1	1	100.00
		i2c_same_csr_outstanding	0.690s	62.401us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.680s	19.843us	1	1	100.00
		i2c_csr_rw	0.700s	26.182us	1	1	100.00
		i2c_csr_aliasing	0.990s	244.190us	1	1	100.00
		i2c_same_csr_outstanding	0.690s	62.401us	1	1	100.00
V2		TOTAL			35	38	92.11
V2S	tl_intg_err	i2c_tl_intg_err	1.050s	248.625us	1	1	100.00
		i2c_sec_cm	0.880s	69.730us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.050s	248.625us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	20.970s	815.777us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	0.780s	698.994us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	12.070s	982.963us	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			44	50	88.00

Failure Buckets

• UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 2 failures:

  • Test i2c_host_error_intr has 1 failures.

    • 0.i2c_host_error_intr.74256429999645407806600920370718413642989002707129362947853011614586038797794
      Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

        UVM_ERROR @  20713066 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @  20713066 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_host_stress_all has 1 failures.

    • 0.i2c_host_stress_all.77526770640956393139441124910751792953736243313946482032479321866765399184467
      Line 94, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

        UVM_ERROR @ 1162939096 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @ 1162939096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:945) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.12258471663181151051907046169582122460717114389527764383134249062415504180193
      Line 98, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 815777347 ps: (cip_base_vseq.sv:945) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 815777347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.99295619870531948229125869329693764033099396242643897149030211912463010036179
      Line 89, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 982963049 ps: (cip_base_vseq.sv:945) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 982963049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_target_glitch has 1 failures.

    • 0.i2c_target_glitch.5100345435135256363086745347549858155353844381326090107958608202304530417115
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

        UVM_ERROR @ 1124105894 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
        UVM_INFO @ 1124105894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.5424715050343775887675670464655265442324559025474914981819708997676921417947
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @ 698994122 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 13 [0xd])
        UVM_INFO @ 698994122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---