9bb489f| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rv_dm_smoke | 11.590s | 10.177ms | 0 | 1 | 0.00 |
| V1 | jtag_dtm_csr_hw_reset | rv_dm_jtag_dtm_csr_hw_reset | 1.230s | 1.024ms | 1 | 1 | 100.00 |
| V1 | jtag_dtm_csr_rw | rv_dm_jtag_dtm_csr_rw | 1.340s | 408.140us | 1 | 1 | 100.00 |
| V1 | jtag_dtm_csr_bit_bash | rv_dm_jtag_dtm_csr_bit_bash | 5.850s | 6.382ms | 1 | 1 | 100.00 |
| V1 | jtag_dtm_csr_aliasing | rv_dm_jtag_dtm_csr_aliasing | 1.790s | 1.248ms | 1 | 1 | 100.00 |
| V1 | jtag_dmi_csr_hw_reset | rv_dm_jtag_dmi_csr_hw_reset | 7.430s | 7.730ms | 1 | 1 | 100.00 |
| V1 | jtag_dmi_csr_rw | rv_dm_jtag_dmi_csr_rw | 9.460s | 5.120ms | 1 | 1 | 100.00 |
| V1 | jtag_dmi_csr_bit_bash | rv_dm_jtag_dmi_csr_bit_bash | 11.190s | 14.288ms | 1 | 1 | 100.00 |
| V1 | jtag_dmi_csr_aliasing | rv_dm_jtag_dmi_csr_aliasing | 42.390s | 83.702ms | 1 | 1 | 100.00 |
| V1 | jtag_dmi_cmderr_busy | rv_dm_cmderr_busy | 1.080s | 449.535us | 1 | 1 | 100.00 |
| V1 | jtag_dmi_cmderr_not_supported | rv_dm_cmderr_not_supported | 1.220s | 119.258us | 1 | 1 | 100.00 |
| V1 | cmderr_exception | rv_dm_cmderr_exception | 2.180s | 633.343us | 1 | 1 | 100.00 |
| V1 | mem_tl_access_resuming | rv_dm_mem_tl_access_resuming | 1.280s | 229.310us | 1 | 1 | 100.00 |
| V1 | mem_tl_access_halted | rv_dm_mem_tl_access_halted | 1.400s | 353.338us | 1 | 1 | 100.00 |
| V1 | cmderr_halt_resume | rv_dm_cmderr_halt_resume | 1.860s | 556.387us | 1 | 1 | 100.00 |
| V1 | dataaddr_rw_access | rv_dm_dataaddr_rw_access | 0.860s | 228.730us | 1 | 1 | 100.00 |
| V1 | halt_resume | rv_dm_halt_resume_whereto | 1.410s | 414.629us | 1 | 1 | 100.00 |
| V1 | progbuf_busy | rv_dm_cmderr_busy | 1.080s | 449.535us | 1 | 1 | 100.00 |
| V1 | abstractcmd_status | rv_dm_abstractcmd_status | 1.430s | 527.023us | 1 | 1 | 100.00 |
| V1 | progbuf_read_write_execute | rv_dm_progbuf_read_write_execute | 1.250s | 930.941us | 1 | 1 | 100.00 |
| V1 | progbuf_exception | rv_dm_cmderr_exception | 2.180s | 633.343us | 1 | 1 | 100.00 |
| V1 | rom_read_access | rv_dm_rom_read_access | 0.970s | 112.746us | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | rv_dm_csr_hw_reset | 1.770s | 364.683us | 1 | 1 | 100.00 |
| V1 | csr_rw | rv_dm_csr_rw | 2.100s | 314.108us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | rv_dm_csr_bit_bash | 49.710s | 81.189ms | 1 | 1 | 100.00 |
| V1 | csr_aliasing | rv_dm_csr_aliasing | 49.190s | 4.381ms | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_dm_csr_mem_rw_with_rand_reset | 0.910s | 116.590us | 0 | 1 | 0.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_dm_csr_aliasing | 49.190s | 4.381ms | 1 | 1 | 100.00 |
| rv_dm_csr_rw | 2.100s | 314.108us | 1 | 1 | 100.00 | ||
| V1 | mem_walk | rv_dm_mem_walk | 0.910s | 48.858us | 1 | 1 | 100.00 |
| V1 | mem_partial_access | rv_dm_mem_partial_access | 0.990s | 98.660us | 1 | 1 | 100.00 |
| V1 | TOTAL | 25 | 27 | 92.59 | |||
| V2 | idcode | rv_dm_smoke | 11.590s | 10.177ms | 0 | 1 | 0.00 |
| V2 | jtag_dtm_hard_reset | rv_dm_jtag_dtm_hard_reset | 1.540s | 283.177us | 1 | 1 | 100.00 |
| V2 | jtag_dtm_idle_hint | rv_dm_jtag_dtm_idle_hint | 0.970s | 401.356us | 1 | 1 | 100.00 |
| V2 | jtag_dmi_failed_op | rv_dm_dmi_failed_op | 1.220s | 621.553us | 1 | 1 | 100.00 |
| V2 | jtag_dmi_dm_inactive | rv_dm_jtag_dmi_dm_inactive | 1.410s | 334.332us | 1 | 1 | 100.00 |
| V2 | sba | rv_dm_sba_tl_access | 6.184m | 300.000ms | 0 | 1 | 0.00 |
| rv_dm_delayed_resp_sba_tl_access | 5.601m | 300.000ms | 0 | 1 | 0.00 | ||
| V2 | bad_sba | rv_dm_bad_sba_tl_access | 8.017m | 300.000ms | 0 | 1 | 0.00 |
| V2 | sba_autoincrement | rv_dm_autoincr_sba_tl_access | 2.882m | 300.000ms | 0 | 1 | 0.00 |
| V2 | jtag_dmi_debug_disabled | rv_dm_jtag_dmi_debug_disabled | 0.920s | 86.593us | 1 | 1 | 100.00 |
| V2 | sba_debug_disabled | rv_dm_sba_debug_disabled | 6.070s | 6.047ms | 1 | 1 | 100.00 |
| V2 | ndmreset_req | rv_dm_ndmreset_req | 1.250s | 176.538us | 1 | 1 | 100.00 |
| V2 | hart_unavail | rv_dm_hart_unavail | 0.910s | 153.259us | 1 | 1 | 100.00 |
| V2 | tap_ctrl_transitions | rv_dm_tap_fsm | 22.450s | 6.887ms | 1 | 1 | 100.00 |
| rv_dm_tap_fsm_rand_reset | 0.960s | 25.084us | 0 | 1 | 0.00 | ||
| V2 | hartsel_warl | rv_dm_hartsel_warl | 1.500s | 334.445us | 1 | 1 | 100.00 |
| V2 | stress_all | rv_dm_stress_all | 3.210s | 3.905ms | 1 | 1 | 100.00 |
| V2 | alert_test | rv_dm_alert_test | 0.830s | 77.207us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_dm_tl_errors | 0.880s | 57.614us | 0 | 1 | 0.00 |
| V2 | tl_d_illegal_access | rv_dm_tl_errors | 0.880s | 57.614us | 0 | 1 | 0.00 |
| V2 | tl_d_outstanding_access | rv_dm_csr_aliasing | 49.190s | 4.381ms | 1 | 1 | 100.00 |
| rv_dm_csr_hw_reset | 1.770s | 364.683us | 1 | 1 | 100.00 | ||
| rv_dm_csr_rw | 2.100s | 314.108us | 1 | 1 | 100.00 | ||
| rv_dm_same_csr_outstanding | 6.910s | 1.085ms | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | rv_dm_csr_aliasing | 49.190s | 4.381ms | 1 | 1 | 100.00 |
| rv_dm_csr_hw_reset | 1.770s | 364.683us | 1 | 1 | 100.00 | ||
| rv_dm_csr_rw | 2.100s | 314.108us | 1 | 1 | 100.00 | ||
| rv_dm_same_csr_outstanding | 6.910s | 1.085ms | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 13 | 19 | 68.42 | |||
| V2S | tl_intg_err | rv_dm_sec_cm | 2.020s | 434.156us | 1 | 1 | 100.00 |
| rv_dm_tl_intg_err | 15.860s | 7.656ms | 1 | 1 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_dm_tl_intg_err | 15.860s | 7.656ms | 1 | 1 | 100.00 |
| V2S | sec_cm_lc_hw_debug_en_intersig_mubi | rv_dm_sba_debug_disabled | 6.070s | 6.047ms | 1 | 1 | 100.00 |
| rv_dm_debug_disabled | 0.980s | 43.246us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_lc_dft_en_intersig_mubi | rv_dm_sba_debug_disabled | 6.070s | 6.047ms | 1 | 1 | 100.00 |
| rv_dm_debug_disabled | 0.980s | 43.246us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi | rv_dm_smoke | 11.590s | 10.177ms | 0 | 1 | 0.00 |
| V2S | sec_cm_dm_en_ctrl_lc_gated | rv_dm_buffered_enable | 1.740s | 434.540us | 1 | 1 | 100.00 |
| V2S | sec_cm_sba_tl_lc_gate_fsm_sparse | rv_dm_sparse_lc_gate_fsm | 1.090s | 219.581us | 1 | 1 | 100.00 |
| V2S | sec_cm_mem_tl_lc_gate_fsm_sparse | rv_dm_sparse_lc_gate_fsm | 1.090s | 219.581us | 1 | 1 | 100.00 |
| V2S | sec_cm_exec_ctrl_mubi | rv_dm_buffered_enable | 1.740s | 434.540us | 1 | 1 | 100.00 |
| V2S | TOTAL | 5 | 5 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_dm_stress_all_with_rand_reset | 1.190s | 132.307us | 0 | 1 | 0.00 |
| V3 | TOTAL | 0 | 1 | 0.00 | |||
| Unmapped tests | rv_dm_scanmode | 0.690s | 48.536us | 1 | 1 | 100.00 | |
| TOTAL | 44 | 53 | 83.02 |
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:
Test rv_dm_sba_tl_access has 1 failures.
0.rv_dm_sba_tl_access.38665689191600139070999749860299995856275786993665065826606103855704526263396
Line 83, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_delayed_resp_sba_tl_access has 1 failures.
0.rv_dm_delayed_resp_sba_tl_access.14099767694165258188037737908473618009761520524371118158905214837344200424585
Line 83, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_delayed_resp_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_bad_sba_tl_access has 1 failures.
0.rv_dm_bad_sba_tl_access.73061931236895169068501722513776135112389898163643635166639478599548259426569
Line 83, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_bad_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_autoincr_sba_tl_access has 1 failures.
0.rv_dm_autoincr_sba_tl_access.37744087002104849806138794448134016864630312314882637124088410609425433386484
Line 83, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[NOA] Null object access has 1 failures:
0.rv_dm_smoke.107962547970563290928724615037230812713109403562946113301017049799856390000063
Line 85, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_smoke/latest/run.log
Error-[NOA] Null object access
src/lowrisc_dv_cip_lib_0/seq_lib/cip_base_vseq.sv, 290
The object at dereference depth 0 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@5647) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
0.rv_dm_tap_fsm_rand_reset.19170223722578898915565904055694838704485726416015491209276033685740491191914
Line 76, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 25083525 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@5647) { a_addr: 'hfea2d420 a_data: 'hb23b4f38 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hd5 a_opcode: 'h4 a_user: 'h1881b d_param: 'h0 d_source: 'hd5 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 25083525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@17837) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
0.rv_dm_stress_all_with_rand_reset.19544634743773268337938049066887225560552103467256805872867960223911951999859
Line 83, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 132307275 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@17837) { a_addr: 'h189587ec a_data: 'h2a7001d9 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h8 a_opcode: 'h4 a_user: 'h1b5de d_param: 'h0 d_source: 'h8 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 132307275 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@5797) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
0.rv_dm_tl_errors.60845533221057728115516319404228283680103314967134132879989325632016992141337
Line 75, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_tl_errors/latest/run.log
UVM_ERROR @ 57613800 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@5797) { a_addr: 'h7f94a5e4 a_data: 'h95405891 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3 a_opcode: 'h4 a_user: 'h1a236 d_param: 'h0 d_source: 'h3 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 57613800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@5699) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
0.rv_dm_csr_mem_rw_with_rand_reset.64025119379684902515638527802419886704979359283665119584079067767785678697229
Line 76, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 116589645 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@5699) { a_addr: 'h7ba81414 a_data: 'hd23f08f9 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h2e a_opcode: 'h4 a_user: 'h19022 d_param: 'h0 d_source: 'h2e d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 116589645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---