| V1 |
random |
rv_timer_random |
0.820s |
23.660us |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
rv_timer_csr_hw_reset |
0.750s |
100.639us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
rv_timer_csr_rw |
0.740s |
28.090us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
rv_timer_csr_bit_bash |
2.500s |
297.945us |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
rv_timer_csr_aliasing |
0.630s |
58.991us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
rv_timer_csr_mem_rw_with_rand_reset |
0.840s |
231.455us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
rv_timer_csr_rw |
0.740s |
28.090us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_aliasing |
0.630s |
58.991us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
6 |
6 |
100.00 |
| V2 |
random_reset |
rv_timer_random_reset |
0.740s |
468.940us |
1 |
1 |
100.00 |
| V2 |
disabled |
rv_timer_disabled |
0.680s |
236.300us |
1 |
1 |
100.00 |
| V2 |
cfg_update_on_fly |
rv_timer_cfg_update_on_fly |
1.071m |
97.939ms |
1 |
1 |
100.00 |
| V2 |
no_interrupt_test |
rv_timer_cfg_update_on_fly |
1.071m |
97.939ms |
1 |
1 |
100.00 |
| V2 |
stress |
rv_timer_stress_all |
1.710s |
4.678ms |
1 |
1 |
100.00 |
| V2 |
alert_test |
rv_timer_alert_test |
0.720s |
13.959us |
1 |
1 |
100.00 |
| V2 |
intr_test |
rv_timer_intr_test |
0.590s |
136.657us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
rv_timer_tl_errors |
2.020s |
51.480us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
rv_timer_tl_errors |
2.020s |
51.480us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
rv_timer_csr_hw_reset |
0.750s |
100.639us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_rw |
0.740s |
28.090us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_aliasing |
0.630s |
58.991us |
1 |
1 |
100.00 |
|
|
rv_timer_same_csr_outstanding |
0.860s |
21.349us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
rv_timer_csr_hw_reset |
0.750s |
100.639us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_rw |
0.740s |
28.090us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_aliasing |
0.630s |
58.991us |
1 |
1 |
100.00 |
|
|
rv_timer_same_csr_outstanding |
0.860s |
21.349us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
8 |
8 |
100.00 |
| V2S |
tl_intg_err |
rv_timer_sec_cm |
0.950s |
38.055us |
1 |
1 |
100.00 |
|
|
rv_timer_tl_intg_err |
0.950s |
46.262us |
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
rv_timer_tl_intg_err |
0.950s |
46.262us |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
2 |
2 |
100.00 |
| V3 |
min_value |
rv_timer_min |
0.570s |
15.342us |
1 |
1 |
100.00 |
| V3 |
max_value |
rv_timer_max |
0.600s |
10.713us |
1 |
1 |
100.00 |
| V3 |
stress_all_with_rand_reset |
rv_timer_stress_all_with_rand_reset |
5.830s |
953.569us |
1 |
1 |
100.00 |
| V3 |
|
TOTAL |
|
|
3 |
3 |
100.00 |
|
|
TOTAL |
|
|
19 |
19 |
100.00 |