SPI_HOST Simulation Results

Monday September 01 2025 16:38:37 UTC

GitHub Revision: 9bb489f

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	13.000s	711.027us	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	3.000s	20.030us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	3.000s	70.027us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	4.000s	87.011us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	2.000s	52.196us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	3.000s	25.809us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	3.000s	70.027us	1	1	100.00
		spi_host_csr_aliasing	2.000s	52.196us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	3.000s	17.451us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	3.000s	37.330us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	3.000s	32.614us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	24.000s	3.937ms	1	1	100.00
		spi_host_error_cmd	3.000s	48.200us	1	1	100.00
		spi_host_event	14.000s	6.221ms	1	1	100.00
V2	clock_rate	spi_host_speed	4.000s	149.733us	1	1	100.00
V2	speed	spi_host_speed	4.000s	149.733us	1	1	100.00
V2	chip_select_timing	spi_host_speed	4.000s	149.733us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	8.000s	397.834us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	2.000s	58.387us	1	1	100.00
V2	cpol_cpha	spi_host_speed	4.000s	149.733us	1	1	100.00
V2	full_cycle	spi_host_speed	4.000s	149.733us	1	1	100.00
V2	duplex	spi_host_smoke	13.000s	711.027us	1	1	100.00
V2	tx_rx_only	spi_host_smoke	13.000s	711.027us	1	1	100.00
V2	stress_all	spi_host_stress_all	10.000s	620.553us	1	1	100.00
V2	spien	spi_host_spien	6.000s	872.037us	1	1	100.00
V2	stall	spi_host_status_stall	1.133m	5.283ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	5.000s	426.091us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	24.000s	3.937ms	1	1	100.00
V2	alert_test	spi_host_alert_test	3.000s	45.442us	1	1	100.00
V2	intr_test	spi_host_intr_test	3.000s	16.127us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	4.000s	373.208us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	4.000s	373.208us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	3.000s	20.030us	1	1	100.00
		spi_host_csr_rw	3.000s	70.027us	1	1	100.00
		spi_host_csr_aliasing	2.000s	52.196us	1	1	100.00
		spi_host_same_csr_outstanding	3.000s	22.704us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	3.000s	20.030us	1	1	100.00
		spi_host_csr_rw	3.000s	70.027us	1	1	100.00
		spi_host_csr_aliasing	2.000s	52.196us	1	1	100.00
		spi_host_same_csr_outstanding	3.000s	22.704us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	3.000s	87.330us	1	1	100.00
		spi_host_sec_cm	3.000s	335.787us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	3.000s	87.330us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	3.033m	200.000ms	0	1	0.00
		TOTAL			25	26	96.15

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test spi_host_upper_range_clkdiv has 1 failures.

    • 0.spi_host_upper_range_clkdiv.38688944399699341160354471752154370054004400309672163363628647084773692363232
      Line 150, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/0.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---