SYSRST_CTRL Simulation Results

Monday September 01 2025 16:38:37 UTC

GitHub Revision: 9bb489f

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sysrst_ctrl_smoke 4.640s 2.112ms 1 1 100.00
V1 input_output_inverted sysrst_ctrl_in_out_inverted 1.120s 2.554ms 1 1 100.00
V1 combo_detect_ec_rst sysrst_ctrl_combo_detect_ec_rst 5.330s 2.411ms 1 1 100.00
V1 combo_detect_ec_rst_with_pre_cond sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 1.690s 2.274ms 1 1 100.00
V1 csr_hw_reset sysrst_ctrl_csr_hw_reset 12.490s 6.011ms 1 1 100.00
V1 csr_rw sysrst_ctrl_csr_rw 1.110s 2.325ms 1 1 100.00
V1 csr_bit_bash sysrst_ctrl_csr_bit_bash 23.040s 34.539ms 1 1 100.00
V1 csr_aliasing sysrst_ctrl_csr_aliasing 2.750s 2.537ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset sysrst_ctrl_csr_mem_rw_with_rand_reset 1.570s 2.142ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr sysrst_ctrl_csr_rw 1.110s 2.325ms 1 1 100.00
sysrst_ctrl_csr_aliasing 2.750s 2.537ms 1 1 100.00
V1 TOTAL 9 9 100.00
V2 combo_detect sysrst_ctrl_combo_detect 1.794m 97.277ms 1 1 100.00
V2 combo_detect_with_pre_cond sysrst_ctrl_combo_detect_with_pre_cond 13.030s 26.595ms 1 1 100.00
V2 auto_block_key_outputs sysrst_ctrl_auto_blk_key_output 6.440s 3.044ms 1 1 100.00
V2 keyboard_input_triggered_interrupt sysrst_ctrl_edge_detect 2.060s 5.441ms 1 1 100.00
V2 pin_output_keyboard_inversion_control sysrst_ctrl_pin_override_test 1.480s 2.537ms 1 1 100.00
V2 pin_input_value_accessibility sysrst_ctrl_pin_access_test 2.780s 2.171ms 1 1 100.00
V2 ec_power_on_reset sysrst_ctrl_ec_pwr_on_rst 4.340s 4.256ms 1 1 100.00
V2 flash_write_protect_output sysrst_ctrl_flash_wr_prot_out 3.390s 2.618ms 1 1 100.00
V2 ultra_low_power_test sysrst_ctrl_ultra_low_pwr 3.300s 5.889ms 1 1 100.00
V2 sysrst_ctrl_feature_disable sysrst_ctrl_feature_disable 34.920s 36.277ms 1 1 100.00
V2 stress_all sysrst_ctrl_stress_all 18.660s 13.392ms 1 1 100.00
V2 alert_test sysrst_ctrl_alert_test 4.360s 2.009ms 1 1 100.00
V2 intr_test sysrst_ctrl_intr_test 1.470s 2.032ms 1 1 100.00
V2 tl_d_oob_addr_access sysrst_ctrl_tl_errors 6.090s 2.073ms 1 1 100.00
V2 tl_d_illegal_access sysrst_ctrl_tl_errors 6.090s 2.073ms 1 1 100.00
V2 tl_d_outstanding_access sysrst_ctrl_csr_hw_reset 12.490s 6.011ms 1 1 100.00
sysrst_ctrl_csr_rw 1.110s 2.325ms 1 1 100.00
sysrst_ctrl_csr_aliasing 2.750s 2.537ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 6.180s 4.894ms 1 1 100.00
V2 tl_d_partial_access sysrst_ctrl_csr_hw_reset 12.490s 6.011ms 1 1 100.00
sysrst_ctrl_csr_rw 1.110s 2.325ms 1 1 100.00
sysrst_ctrl_csr_aliasing 2.750s 2.537ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 6.180s 4.894ms 1 1 100.00
V2 TOTAL 15 15 100.00
V2S tl_intg_err sysrst_ctrl_sec_cm 23.810s 42.108ms 1 1 100.00
sysrst_ctrl_tl_intg_err 44.540s 22.212ms 1 1 100.00
V2S sec_cm_bus_integrity sysrst_ctrl_tl_intg_err 44.540s 22.212ms 1 1 100.00
V2S TOTAL 2 2 100.00
V3 stress_all_with_rand_reset sysrst_ctrl_stress_all_with_rand_reset 3.440s 2.675ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 27 27 100.00