UART Simulation Results

Monday September 01 2025 16:38:37 UTC

GitHub Revision: 9bb489f

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	1.240s	639.785us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.580s	48.517us	1	1	100.00
V1	csr_rw	uart_csr_rw	0.550s	13.547us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.900s	1.020ms	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	0.750s	32.144us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	0.790s	26.257us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.550s	13.547us	1	1	100.00
		uart_csr_aliasing	0.750s	32.144us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	49.480s	160.987ms	1	1	100.00
V2	parity	uart_smoke	1.240s	639.785us	1	1	100.00
		uart_tx_rx	49.480s	160.987ms	1	1	100.00
V2	parity_error	uart_intr	1.665m	102.271ms	1	1	100.00
		uart_rx_parity_err	17.830s	15.994ms	1	1	100.00
V2	watermark	uart_tx_rx	49.480s	160.987ms	1	1	100.00
		uart_intr	1.665m	102.271ms	1	1	100.00
V2	fifo_full	uart_fifo_full	36.870s	80.079ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	14.810s	51.027ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	32.860s	28.592ms	1	1	100.00
V2	rx_frame_err	uart_intr	1.665m	102.271ms	1	1	100.00
V2	rx_break_err	uart_intr	1.665m	102.271ms	1	1	100.00
V2	rx_timeout	uart_intr	1.665m	102.271ms	1	1	100.00
V2	perf	uart_perf	4.362m	17.929ms	1	1	100.00
V2	sys_loopback	uart_loopback	19.210s	8.581ms	1	1	100.00
V2	line_loopback	uart_loopback	19.210s	8.581ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	3.500s	1.420ms	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	3.790s	2.544ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	2.250s	2.865ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	11.510s	2.448ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	4.174m	140.961ms	1	1	100.00
V2	stress_all	uart_stress_all	1.195m	39.744ms	0	1	0.00
V2	alert_test	uart_alert_test	0.780s	14.117us	1	1	100.00
V2	intr_test	uart_intr_test	0.570s	15.276us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.640s	241.635us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.640s	241.635us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.580s	48.517us	1	1	100.00
		uart_csr_rw	0.550s	13.547us	1	1	100.00
		uart_csr_aliasing	0.750s	32.144us	1	1	100.00
		uart_same_csr_outstanding	0.680s	72.400us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.580s	48.517us	1	1	100.00
		uart_csr_rw	0.550s	13.547us	1	1	100.00
		uart_csr_aliasing	0.750s	32.144us	1	1	100.00
		uart_same_csr_outstanding	0.680s	72.400us	1	1	100.00
V2		TOTAL			16	18	88.89
V2S	tl_intg_err	uart_sec_cm	1.060s	82.384us	1	1	100.00
		uart_tl_intg_err	1.280s	97.805us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.280s	97.805us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	33.530s	16.909ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			25	27	92.59

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 1 failures:

  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.89382724173337680238553102281794607237566211162435589882944039765058367848810
      Line 71, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @ 153017491 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0
        UVM_ERROR @ 153027592 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 153037693 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata
        UVM_ERROR @ 350310223 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 350310223 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
      

• UVM_ERROR (uart_scoreboard.sv:377) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * has 1 failures:

  • Test uart_stress_all has 1 failures.

    • 0.uart_stress_all.93253956595583072566699056490676966117879118219531902132787943940721007438814
      Line 86, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_stress_all/latest/run.log

        UVM_ERROR @ 39331919099 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 39331919099 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 39331919099 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
        UVM_ERROR @ 39418001055 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 3,                                 clk_pulses: 0
        UVM_ERROR @ 39418042721 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (250 [0xfa] vs 95 [0x5f]) reg name: uart_reg_block.rdata