CHIP Simulation Results

Monday September 01 2025 16:38:37 UTC

GitHub Revision: `9bb489f`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	1.859m	2.791ms	1	1	100.00
		chip_sw_example_rom	1.127m	2.960ms	1	1	100.00
		chip_sw_example_manufacturer	2.107m	2.290ms	1	1	100.00
		chip_sw_example_concurrency	2.536m	3.064ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	4.460m	7.596ms	1	1	100.00
V1	csr_rw	chip_csr_rw	5.766m	6.086ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	1.041h	57.562ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	1.142h	36.041ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	46.240s	2.583ms	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	1.142h	36.041ms	1	1	100.00
		chip_csr_rw	5.766m	6.086ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	5.190s	171.464us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	3.967m	3.573ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	3.967m	3.573ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	3.967m	3.573ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	5.616m	3.801ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	5.616m	3.801ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	5.559m	4.578ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	5.674m	3.884ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	6.023m	4.647ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	4.501m	3.609ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	7.544m	4.787ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	17.914m	12.970ms	1	1	100.00
V1		TOTAL			17	18	94.44
V2	chip_pin_mux	chip_padctrl_attributes	2.655m	4.778ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.655m	4.778ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	2.777m	3.242ms	1	1	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	5.145m	5.234ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.605m	2.988ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	8.234m	8.069ms	1	1	100.00
		chip_tap_straps_testunlock0	1.373m	2.528ms	1	1	100.00
		chip_tap_straps_rma	12.687m	11.296ms	1	1	100.00
		chip_tap_straps_prod	5.103m	4.814ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	2.282m	3.367ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	12.167m	8.889ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	6.472m	4.953ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	6.472m	4.953ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	9.785m	7.127ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	30.011m	18.227ms	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	6.232m	4.412ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.965m	6.225ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	57.323m	18.477ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	1.966m	3.143ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	10.958m	7.020ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	3.090m	3.433ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	12.949m	8.272ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.333m	3.033ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	6.468m	5.132ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.315m	3.054ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	3.510m	3.682ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	8.694m	7.959ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	5.671m	5.847ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	2.442m	2.570ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	5.671m	5.847ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	2.153m	3.502ms	1	1	100.00
		chip_sw_aes_smoketest	3.047m	2.919ms	1	1	100.00
		chip_sw_aon_timer_smoketest	2.942m	2.898ms	1	1	100.00
		chip_sw_clkmgr_smoketest	1.848m	2.222ms	1	1	100.00
		chip_sw_csrng_smoketest	2.218m	2.329ms	1	1	100.00
		chip_sw_entropy_src_smoketest	14.041m	8.226ms	1	1	100.00
		chip_sw_gpio_smoketest	2.507m	3.432ms	1	1	100.00
		chip_sw_hmac_smoketest	3.387m	3.265ms	1	1	100.00
		chip_sw_kmac_smoketest	3.117m	3.343ms	1	1	100.00
		chip_sw_otbn_smoketest	21.267m	11.132ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	5.125m	5.818ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	3.697m	5.467ms	1	1	100.00
		chip_sw_rv_plic_smoketest	1.871m	2.665ms	1	1	100.00
		chip_sw_rv_timer_smoketest	2.806m	2.455ms	1	1	100.00
		chip_sw_rstmgr_smoketest	2.492m	3.115ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	1.500m	2.912ms	1	1	100.00
		chip_sw_uart_smoketest	2.594m	2.625ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	2.455m	2.968ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	5.169m	4.422ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	2.136h	61.023ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	42.993m	16.751ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	3.042m	6.720ms	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	3.138m	2.973ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	3.665m	3.110ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.998h	54.757ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.998h	57.648ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	40.710s	1.919ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	40.710s	1.919ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	1.142h	36.041ms	1	1	100.00
		chip_same_csr_outstanding	16.821m	14.881ms	1	1	100.00
		chip_csr_hw_reset	4.460m	7.596ms	1	1	100.00
		chip_csr_rw	5.766m	6.086ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	1.142h	36.041ms	1	1	100.00
		chip_same_csr_outstanding	16.821m	14.881ms	1	1	100.00
		chip_csr_hw_reset	4.460m	7.596ms	1	1	100.00
		chip_csr_rw	5.766m	6.086ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	17.660s	774.141us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	5.810s	35.757us	1	1	100.00
		xbar_smoke_large_delays	1.030m	9.147ms	1	1	100.00
		xbar_smoke_slow_rsp	47.300s	4.999ms	1	1	100.00
		xbar_random_zero_delays	35.700s	570.059us	1	1	100.00
		xbar_random_large_delays	3.030m	31.600ms	1	1	100.00
		xbar_random_slow_rsp	5.271m	36.332ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	8.870s	96.629us	1	1	100.00
		xbar_error_and_unmapped_addr	5.550s	37.240us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	16.250s	327.237us	1	1	100.00
		xbar_error_and_unmapped_addr	5.550s	37.240us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	16.140s	299.932us	1	1	100.00
		xbar_access_same_device_slow_rsp	9.359m	63.444ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	35.080s	1.838ms	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	1.894m	5.025ms	1	1	100.00
		xbar_stress_all_with_error	4.434m	12.598ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	6.983m	5.184ms	1	1	100.00
		xbar_stress_all_with_reset_error	53.430s	363.217us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	42.993m	16.751ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	5.843m	9.632ms	0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	40.630m	15.209ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	34.617m	11.503ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	42.529m	15.798ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	41.855m	15.808ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	43.035m	16.115ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	40.178m	15.297ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	18.220s	10.100us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	22.770s	10.100us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	17.250s	10.180us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	17.210s	10.120us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	22.450s	10.400us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	18.540s	10.360us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	16.780s	10.380us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	20.440s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	16.980s	10.160us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	20.880s	10.180us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	16.750s	10.160us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	16.290s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	18.090s	10.160us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	17.510s	10.280us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	16.720s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	20.460s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	16.270s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	22.060s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	17.060s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	16.420s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	15.890s	10.320us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	16.270s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	19.890s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	18.570s	10.180us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	16.440s	10.260us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	32.337m	11.552ms	1	1	100.00
		rom_e2e_asm_init_dev	42.136m	15.712ms	1	1	100.00
		rom_e2e_asm_init_prod	41.562m	15.889ms	1	1	100.00
		rom_e2e_asm_init_prod_end	41.669m	15.627ms	1	1	100.00
		rom_e2e_asm_init_rma	39.241m	15.269ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	38.352m	16.556ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	40.797m	15.707ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	38.658m	14.675ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	42.202m	16.173ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	50.013m	34.630ms	0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	50.013m	34.630ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.385m	3.291ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	1.966m	3.143ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	2.568m	2.433ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	2.882m	2.465ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	15.274m	7.746ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	1.994m	2.047ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	4.107m	4.166ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	6.255m	5.595ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	8.458m	5.175ms	1	1	100.00
		chip_plic_all_irqs_10	5.308m	3.775ms	1	1	100.00
		chip_plic_all_irqs_20	6.319m	4.534ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	2.931m	2.691ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	14.344m	9.649ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	4.184m	5.226ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	2.608m	2.556ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	12.886m	11.958ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	20.463m	9.631ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	16.415m	7.806ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	13.412m	7.792ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	2.065h	254.152ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	4.711m	4.426ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	5.125m	5.818ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	4.711m	4.426ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	10.657m	10.124ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	10.657m	10.124ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	4.547m	6.106ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	5.766m	4.569ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	8.966m	5.476ms	1	1	100.00
		chip_sw_aes_idle	2.882m	2.465ms	1	1	100.00
		chip_sw_hmac_enc_idle	3.373m	2.856ms	1	1	100.00
		chip_sw_kmac_idle	2.354m	2.464ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	5.713m	4.994ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	3.521m	4.273ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	4.311m	4.382ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	3.705m	4.000ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	11.234m	9.291ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	6.910m	4.077ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.886m	4.600ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.019m	4.440ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.628m	4.435ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	7.222m	4.040ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.607m	4.189ms	1	1	100.00
		chip_sw_ast_clk_outputs	9.785m	7.127ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	3.589m	5.662ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.019m	4.440ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.628m	4.435ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	6.232m	4.412ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.965m	6.225ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	57.323m	18.477ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	1.966m	3.143ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	10.958m	7.020ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	3.090m	3.433ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	12.949m	8.272ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.333m	3.033ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	6.468m	5.132ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.315m	3.054ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	2.364m	3.059ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	7.167m	5.311ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	10.365m	7.296ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	50.457m	24.739ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	3.216m	2.867ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.650m	3.445ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	17.656m	12.100ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	3.168m	3.802ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	5.208m	4.594ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	18.567m	18.865ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	31.638m	15.950ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	9.785m	7.127ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	6.282m	4.635ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	3.796m	2.705ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	6.255m	5.595ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	20.463m	9.631ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	15.874m	7.204ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	3.638m	3.604ms	1	1	100.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	6.084m	5.244ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	3.120m	3.307ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	1.021h	20.730ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	2.265m	2.909ms	1	1	100.00
		chip_sw_edn_entropy_reqs	9.884m	6.379ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	2.265m	2.909ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	15.874m	7.204ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	2.305m	2.527ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	18.197m	19.179ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	10.364m	5.522ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.965m	6.225ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	6.150m	3.941ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	6.232m	4.412ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	58.301m	42.840ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	18.197m	19.179ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	3.486m	3.186ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	19.971m	9.677ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.291m	3.907ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	58.301m	42.840ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.291m	3.907ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.291m	3.907ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	4.291m	3.907ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.291m	3.907ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	6.255m	5.595ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	4.341m	8.847ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	8.809m	5.521ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	6.561m	6.225ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	6.561m	6.225ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	2.520m	3.389ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	3.090m	3.433ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	3.373m	2.856ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	2.136m	2.377ms	0	1	0.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	5.111m	3.608ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	7.735m	5.604ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	7.529m	5.048ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	7.148m	5.279ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	4.431m	4.114ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	19.971m	9.677ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	12.949m	8.272ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	11.287m	6.519ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	15.274m	7.746ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	35.180m	12.720ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	2.772m	2.453ms	1	1	100.00
		chip_sw_kmac_mode_kmac	2.589m	2.727ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.333m	3.033ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	19.971m	9.677ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	7.126m	8.867ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	2.333m	3.142ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	12.611m	5.925ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	2.354m	2.464ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	4.107m	4.166ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	8.234m	8.069ms	1	1	100.00
		chip_tap_straps_rma	12.687m	11.296ms	1	1	100.00
		chip_tap_straps_prod	5.103m	4.814ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.545m	3.002ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	7.126m	8.867ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	7.126m	8.867ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	7.126m	8.867ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	24.397m	12.256ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	4.291m	3.907ms	1	1	100.00
		chip_sw_flash_rma_unlocked	58.301m	42.840ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	2.975m	3.181ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	7.199m	6.596ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	6.912m	5.960ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	7.339m	6.844ms	1	1	100.00
		chip_sw_lc_ctrl_transition	7.126m	8.867ms	1	1	100.00
		chip_sw_keymgr_key_derivation	19.971m	9.677ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	5.514m	9.550ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	9.002m	8.545ms	1	1	100.00
		chip_prim_tl_access	4.341m	8.847ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	3.589m	5.662ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	6.910m	4.077ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.886m	4.600ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.019m	4.440ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.628m	4.435ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	7.222m	4.040ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.607m	4.189ms	1	1	100.00
		chip_tap_straps_dev	8.234m	8.069ms	1	1	100.00
		chip_tap_straps_rma	12.687m	11.296ms	1	1	100.00
		chip_tap_straps_prod	5.103m	4.814ms	1	1	100.00
		chip_rv_dm_lc_disabled	5.179m	11.015ms	1	1	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.303m	3.588ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.575m	3.754ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.301m	3.303ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	2.139m	3.099ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	24.389m	28.158ms	1	1	100.00
		chip_rv_dm_lc_disabled	5.179m	11.015ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.097h	47.520ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	1.117h	47.062ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	7.716m	7.301ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	58.713m	44.814ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	24.389m	28.158ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.087m	2.324ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.162m	2.306ms	1	1	100.00
		rom_volatile_raw_unlock	1.023m	2.446ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	55.170m	17.120ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	57.323m	18.477ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	8.966m	5.476ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	8.966m	5.476ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	8.966m	5.476ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	5.567m	3.838ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	7.126m	8.867ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	18.197m	19.179ms	1	1	100.00
		chip_sw_otbn_mem_scramble	5.567m	3.838ms	1	1	100.00
		chip_sw_keymgr_key_derivation	19.971m	9.677ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	7.005m	4.928ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	1.637m	2.696ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	18.197m	19.179ms	1	1	100.00
		chip_sw_otbn_mem_scramble	5.567m	3.838ms	1	1	100.00
		chip_sw_keymgr_key_derivation	19.971m	9.677ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	7.005m	4.928ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	1.637m	2.696ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	7.126m	8.867ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	4.156m	4.416ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.545m	3.002ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	2.975m	3.181ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	7.199m	6.596ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	6.912m	5.960ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	7.339m	6.844ms	1	1	100.00
		chip_sw_lc_ctrl_transition	7.126m	8.867ms	1	1	100.00
		chip_prim_tl_access	4.341m	8.847ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	4.341m	8.847ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	18.209m	9.712ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	3.890m	7.009ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	20.747m	26.602ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	4.614m	7.388ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	7.005m	7.957ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	4.652m	6.899ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	15.408m	22.687ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	12.363m	15.453ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	10.657m	10.124ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	11.506m	11.442ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	5.728m	4.132ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	3.890m	7.009ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	2.931m	3.784ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	34.376m	32.119ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	4.785m	6.056ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	4.984m	6.017ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	18.647m	22.764ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	9.220m	7.401ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	10.429m	8.756ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	20.604m	26.277ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	2.745m	3.700ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	6.255m	5.595ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	5.514m	9.550ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	5.514m	9.550ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	10.429m	8.756ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	18.647m	22.764ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	5.728m	4.132ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	5.125m	5.818ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	3.583m	4.117ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	5.036m	4.683ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	2.715m	3.183ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	14.344m	9.649ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	3.429m	3.278ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	6.255m	5.595ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	16.415m	7.806ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.995m	4.813ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	7.149m	4.543ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	2.575m	2.875ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	1.637m	2.696ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	5.036m	4.683ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	5.036m	4.683ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	13.691m	12.384ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	15.629m	13.497ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	3.583m	4.117ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	4.194m	3.817ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	3.366m	5.489ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	12.687m	11.296ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	5.179m	11.015ms	1	1	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	8.458m	5.175ms	1	1	100.00
		chip_plic_all_irqs_10	5.308m	3.775ms	1	1	100.00
		chip_plic_all_irqs_20	6.319m	4.534ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	2.144m	2.916ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	2.251m	3.252ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	42.993m	16.751ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	4.867m	5.000ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	2.600m	3.219ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	3.682m	2.953ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	2.684m	2.789ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	7.005m	4.928ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	6.468m	5.132ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	7.756m	7.401ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	5.757m	7.232ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	9.002m	8.545ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	6.255m	5.595ms	1	1	100.00
		chip_sw_data_integrity_escalation	6.472m	4.953ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	9.220m	7.401ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	15.166m	21.845ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	2.226m	2.342ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	3.038m	3.889ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	5.337m	4.643ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	15.166m	21.845ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	15.166m	21.845ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	11.559m	11.542ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	11.559m	11.542ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	3.947m	6.583ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	50.013m	34.630ms	0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	2.131m	3.422ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	2.455m	2.508ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	4.302m	4.081ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	5.463m	4.286ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	18.461m	8.332ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.378h	31.956ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	31.748m	12.877ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	2.507m	2.861ms	1	1	100.00
V2		TOTAL			238	275	86.55
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	2.270m	2.874ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	1.484m	2.243ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_sw_coremark	chip_sw_coremark	2.560h	72.255ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	6.468m	3.804ms	0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	18.990m	11.208ms	1	1	100.00
		rom_e2e_jtag_debug_dev	10.574m	7.656ms	0	1	0.00
		rom_e2e_jtag_debug_rma	2.503m	3.634ms	0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	2.717m	4.395ms	1	1	100.00
		rom_e2e_jtag_inject_dev	3.109m	5.216ms	1	1	100.00
		rom_e2e_jtag_inject_rma	2.779m	4.724ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	10.425s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	8.662m	4.929ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	4.842m	2.607ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	19.072m	7.313ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	23.022m	9.174ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.274m	2.339ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	9.649m	5.059ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	48.760s	1.737ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	6.269m	5.051ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	3.797m	6.135ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	5.686m	4.978ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	10.429m	8.756ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	18.990m	11.208ms	1	1	100.00
		rom_e2e_jtag_debug_dev	10.574m	7.656ms	0	1	0.00
		rom_e2e_jtag_debug_rma	2.503m	3.634ms	0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	5.755m	4.862ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	6.255m	5.595ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.503h	37.916ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.503h	37.916ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	2.595m	3.069ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	5.616m	3.801ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	51.422m	18.989ms	1	1	100.00
V3		TOTAL			19	23	82.61
	Unmapped tests	chip_sival_flash_info_access	2.530m	3.190ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	5.752m	5.568ms	1	1	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	2.016m	2.608ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	4.035m	3.564ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	2.870m	3.599ms	0	1	0.00
		chip_sw_pwrmgr_sleep_wake_5_bug	9.067s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	3.626m	3.318ms	1	1	100.00
		TOTAL			281	325	86.46

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.69719481480811008567588065296654779663996065133935874047166838126536867782590
    Line 503, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.41785357970716716964314856416697934588383646415820061077190996251139720687101
    Line 506, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.23212597136055773078039202323227250615354700986546544130581148795216811454890
    Line 505, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.78456304964375082055052001838930445198748765026240725102304113748153188085561
    Line 517, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.99874126222761156169501736162708145856605474684997013219094073230536818733405
    Line 495, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.44259076821836892279401177958157388362237073986288662805026685753209164729839
    Line 486, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.61489075734729381804779144909122767405998867832149998198194300697417014200210
    Line 478, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.76179429891502097091921496454445696026023098826422683773183542564137782719193
    Line 467, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.33686583653325132090938770103038893119897051258428743818861915570106235477494
    Line 469, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.83908283090346736552612960472159354120636798636436733314050655341824516504262
    Line 498, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.68982194682082405535904697458530520052239021084035823385471557982572924391273
    Line 448, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.5455806853878170859585333855337151544717777057884349216034348841563499140849
    Line 497, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.12892254621986751797288181372421607997633216583710406905589367113534981837910
    Line 482, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.8612396966134268823207033155610754796897433388163337615275422716245576427692
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.169s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.38997826152292501485551088363746417693547144543688738230021901562215841197489
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 0.457s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.44202554764811805287392356492241963364626526383908593277834400348716413888253
    Line 480, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.74727688260516266805204116861210577985006032814810062395594437667422566900595
    Line 485, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.34592064284330300528845477666104139611719729767892408823468864983316028906995
    Line 554, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.5407052263711809613611605124648292947814662156627482717478904299257482003282
    Line 482, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.94206610855901814839858642708467619529364576229925995243038096721295491702174
    Line 396, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3219.167620 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 3219.167620 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@109068) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.36715308992614375124378544769392848148195025231870694082151764535514793692136
Line 416, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 4683.448552 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@109068) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4683.448552 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:200)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor has 1 failures:
- Test chip_sw_sysrst_ctrl_ec_rst_l has 1 failures.
  - 0.chip_sw_sysrst_ctrl_ec_rst_l.34033936292924586430749592353886469453401623654509582819442879707380939433360
    Line 398, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_ec_rst_l/latest/run.log
```
  UVM_ERROR @ 11542.125400 us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:200)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor
  UVM_INFO @ 11542.125400 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 1 failures.
  - 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.87211778253582506071159635780782838542249151779940803631352959184611737821028
    Line 411, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  UVM_ERROR @ 34629.793103 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 34629.793103 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:292)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.109133547524432929089132882430304673956344802914594961899649297124040564057104
    Line 387, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 2047.428298 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:292)] CHECK-fail: Expect alert 28!
  UVM_INFO @ 2047.428298 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.5917175762117131799533230934323497169582797699541476493572379691476771315894
    Line 387, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 2556.245158 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 2556.245158 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: *. has 1 failures:
- Test chip_sw_hmac_oneshot has 1 failures.
  - 0.chip_sw_hmac_oneshot.109653465849664124311511780574980966804453558445413712669310522608688713133306
    Line 389, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_oneshot/latest/run.log
```
  UVM_ERROR @ 2376.616920 us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: 8000534a.
  UVM_INFO @ 2376.616920 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@36990) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.59299124527200795921787460747647978707062521129851407382559021038053521427192
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 1919.082180 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@36990) { a_addr: 'h1034c  a_data: 'he3f96009  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h39  a_opcode: 'h4  a_user: 'h1ba3c  d_param: 'h0  d_source: 'h39  d_data: 'h13  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd7d  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 1919.082180 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:78)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for !get_wakeup_status() has 1 failures:
- Test chip_sw_pwrmgr_lowpower_cancel has 1 failures.
  - 0.chip_sw_pwrmgr_lowpower_cancel.32037801580926163848038854645952715883672562966782394553376659676525193332368
    Line 399, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_lowpower_cancel/latest/run.log
```
  UVM_ERROR @ 3599.263520 us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:78)] CHECK-fail: Timed out after 100 usec (10000 CPU cycles) waiting for !get_wakeup_status()
  UVM_INFO @ 3599.263520 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.6349134380925076122804953299607862148295925841828209985628371559486257028601
    Line 393, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 2972.676000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 2972.676000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.62285809711540694748782987289758818183551460946512200436617255911132515042889
    Line 399, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 3109.735000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3109.735000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.32519768096194657903127715240727100136678785267325104296368923536648958013031
    Line 412, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 18227.040543 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 18227.040543 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:196) [chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= * (* [*] vs * [*]) has 1 failures:
- Test chip_sw_power_virus has 1 failures.
  - 0.chip_sw_power_virus.40199354336886800770753217505775227399421861087760794328160902191122969800067
    Line 439, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 3804.480579 us: (chip_sw_power_virus_vseq.sv:196) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 3804.480579 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(pend_req[h2d.a_source].pend == *)' has 1 failures:
- Test rom_e2e_shutdown_output has 1 failures.
  - 0.rom_e2e_shutdown_output.16563129428543040481881816498407280324358379862509510178392330106975523203591
    Line 424, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_shutdown_output/latest/run.log
```
      Offending '(pend_req[h2d.a_source].pend == 0)'
  UVM_ERROR @ 9632.158563 us: (tlul_assert.sv:283) [ASSERT FAILED] pendingReqPerSrc_M
  UVM_INFO @ 9632.158563 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.101545833762545412468432481857465894229196437750210737026018431225208051877465
    Line 453, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.91358158417921183190286102103183961998022988113111709218450791965359817924075
    Line 486, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_rom_e2e_jtag_debug_vseq.sv:260) [chip_sw_rom_e2e_jtag_debug_vseq] Check failed value_q[*] == test_data[i] (* [*] vs * [*]) for addr * has 1 failures:
- Test rom_e2e_jtag_debug_dev has 1 failures.
  - 0.rom_e2e_jtag_debug_dev.57174992423035698826904601868151098316457147539377308571164755248841319396952
    Line 454, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log
```
  UVM_ERROR @ 7656.485660 us: (chip_sw_rom_e2e_jtag_debug_vseq.sv:260) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_jtag_debug_vseq] Check failed value_q[0] == test_data[i] (944425022 [0x384ac83e] vs 1129400596 [0x43514914]) for addr 0x10019618
  UVM_INFO @ 7656.485660 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (jtag_rv_debugger.sv:784) [debugger] Index * appears to be out of bounds has 1 failures:
- Test rom_e2e_jtag_debug_rma has 1 failures.
  - 0.rom_e2e_jtag_debug_rma.20931175244319358602318213742080054628299060607868839628757011404736560497640
    Line 425, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log
```
  UVM_ERROR @ 3634.210291 us: (jtag_rv_debugger.sv:784) [debugger] Index 3 appears to be out of bounds
  UVM_INFO @ 3634.210291 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31786) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

0.chip_csr_mem_rw_with_rand_reset.20146927558971275237120122903318757906756912217574895593963363864092352463896
Line 221, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2583.415312 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31786) { a_addr: 'h1070c  a_data: 'hc05513ab  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1  a_opcode: 'h4  a_user: 'h181ed  d_param: 'h0  d_source: 'h1  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2583.415312 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---