ADC_CTRL Simulation Results

Tuesday September 02 2025 17:05:38 UTC

GitHub Revision: a14e715

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	12.810s	6.143ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	1.190s	800.056us	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	0.770s	629.424us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	15.590s	26.453ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	1.440s	739.922us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	1.660s	562.872us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	0.770s	629.424us	1	1	100.00
		adc_ctrl_csr_aliasing	1.440s	739.922us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	2.502m	331.389ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	5.063m	324.832ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	5.073m	168.010ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	3.900m	484.469ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	15.332m	571.192ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	5.229m	191.521ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	5.215m	331.930ms	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	11.679m	495.528ms	1	1	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	2.330s	3.312ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.071m	40.403ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	18.110s	84.047ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	4.599m	172.676ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	1.850s	433.972us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	1.080s	432.340us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	2.560s	641.196us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	2.560s	641.196us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	1.190s	800.056us	1	1	100.00
		adc_ctrl_csr_rw	0.770s	629.424us	1	1	100.00
		adc_ctrl_csr_aliasing	1.440s	739.922us	1	1	100.00
		adc_ctrl_same_csr_outstanding	3.730s	4.563ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	1.190s	800.056us	1	1	100.00
		adc_ctrl_csr_rw	0.770s	629.424us	1	1	100.00
		adc_ctrl_csr_aliasing	1.440s	739.922us	1	1	100.00
		adc_ctrl_same_csr_outstanding	3.730s	4.563ms	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	tl_intg_err	adc_ctrl_sec_cm	3.580s	4.129ms	1	1	100.00
		adc_ctrl_tl_intg_err	5.510s	8.631ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	5.510s	8.631ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	8.810s	2.211ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			25	25	100.00