| V1 |
smoke |
aon_timer_smoke |
0.780s |
726.050us |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
aon_timer_csr_hw_reset |
1.460s |
872.652us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
aon_timer_csr_rw |
0.740s |
386.429us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
aon_timer_csr_bit_bash |
7.880s |
7.404ms |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
aon_timer_csr_aliasing |
0.860s |
387.802us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
aon_timer_csr_mem_rw_with_rand_reset |
0.900s |
536.556us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
aon_timer_csr_rw |
0.740s |
386.429us |
1 |
1 |
100.00 |
|
|
aon_timer_csr_aliasing |
0.860s |
387.802us |
1 |
1 |
100.00 |
| V1 |
mem_walk |
aon_timer_mem_walk |
0.650s |
533.951us |
1 |
1 |
100.00 |
| V1 |
mem_partial_access |
aon_timer_mem_partial_access |
0.780s |
401.335us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
8 |
8 |
100.00 |
| V2 |
prescaler |
aon_timer_prescaler |
2.650s |
6.647ms |
1 |
1 |
100.00 |
| V2 |
jump |
aon_timer_jump |
0.750s |
612.756us |
1 |
1 |
100.00 |
| V2 |
stress_all |
aon_timer_stress_all |
9.800s |
64.652ms |
1 |
1 |
100.00 |
| V2 |
alert_test |
aon_timer_alert_test |
0.950s |
352.071us |
1 |
1 |
100.00 |
| V2 |
intr_test |
aon_timer_intr_test |
0.840s |
486.003us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
aon_timer_tl_errors |
1.100s |
682.164us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
aon_timer_tl_errors |
1.100s |
682.164us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
aon_timer_csr_hw_reset |
1.460s |
872.652us |
1 |
1 |
100.00 |
|
|
aon_timer_csr_rw |
0.740s |
386.429us |
1 |
1 |
100.00 |
|
|
aon_timer_csr_aliasing |
0.860s |
387.802us |
1 |
1 |
100.00 |
|
|
aon_timer_same_csr_outstanding |
1.690s |
1.207ms |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
aon_timer_csr_hw_reset |
1.460s |
872.652us |
1 |
1 |
100.00 |
|
|
aon_timer_csr_rw |
0.740s |
386.429us |
1 |
1 |
100.00 |
|
|
aon_timer_csr_aliasing |
0.860s |
387.802us |
1 |
1 |
100.00 |
|
|
aon_timer_same_csr_outstanding |
1.690s |
1.207ms |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
7 |
7 |
100.00 |
| V2S |
tl_intg_err |
aon_timer_sec_cm |
5.320s |
4.252ms |
1 |
1 |
100.00 |
|
|
aon_timer_tl_intg_err |
5.450s |
4.728ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
aon_timer_tl_intg_err |
5.450s |
4.728ms |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
2 |
2 |
100.00 |
| V3 |
max_threshold |
aon_timer_smoke_max_thold |
0.700s |
513.054us |
1 |
1 |
100.00 |
| V3 |
min_threshold |
aon_timer_smoke_min_thold |
1.130s |
621.055us |
1 |
1 |
100.00 |
| V3 |
wkup_count_hi_cdc |
aon_timer_wkup_count_cdc_hi |
6.590s |
3.599ms |
1 |
1 |
100.00 |
| V3 |
custom_intr |
aon_timer_custom_intr |
0.720s |
579.422us |
1 |
1 |
100.00 |
| V3 |
alternating_on_off |
aon_timer_alternating_enable_on_off |
3.710s |
4.287ms |
1 |
1 |
100.00 |
| V3 |
stress_all_with_rand_reset |
aon_timer_stress_all_with_rand_reset |
28.750s |
22.997ms |
1 |
1 |
100.00 |
| V3 |
|
TOTAL |
|
|
6 |
6 |
100.00 |
|
|
TOTAL |
|
|
23 |
23 |
100.00 |