EDN Simulation Results

Tuesday September 02 2025 17:05:38 UTC

GitHub Revision: a14e715

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	0.870s	49.981us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.810s	18.322us	1	1	100.00
V1	csr_rw	edn_csr_rw	0.810s	16.595us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	2.230s	114.133us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	1.320s	81.911us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.030s	189.023us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.810s	16.595us	1	1	100.00
		edn_csr_aliasing	1.320s	81.911us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	0.930s	41.826us	1	1	100.00
V2	csrng_commands	edn_genbits	0.930s	41.826us	1	1	100.00
V2	genbits	edn_genbits	0.930s	41.826us	1	1	100.00
V2	interrupts	edn_intr	0.910s	28.210us	1	1	100.00
V2	alerts	edn_alert	0.950s	44.664us	1	1	100.00
V2	errs	edn_err	1.210s	30.316us	1	1	100.00
V2	disable	edn_disable	0.850s	11.368us	1	1	100.00
		edn_disable_auto_req_mode	0.980s	120.693us	1	1	100.00
V2	stress_all	edn_stress_all	0.830s	73.861us	1	1	100.00
V2	intr_test	edn_intr_test	0.820s	35.986us	1	1	100.00
V2	alert_test	edn_alert_test	0.730s	44.504us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	3.070s	216.609us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	3.070s	216.609us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.810s	18.322us	1	1	100.00
		edn_csr_rw	0.810s	16.595us	1	1	100.00
		edn_csr_aliasing	1.320s	81.911us	1	1	100.00
		edn_same_csr_outstanding	1.020s	64.136us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.810s	18.322us	1	1	100.00
		edn_csr_rw	0.810s	16.595us	1	1	100.00
		edn_csr_aliasing	1.320s	81.911us	1	1	100.00
		edn_same_csr_outstanding	1.020s	64.136us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	7.020s	1.874ms	1	1	100.00
		edn_tl_intg_err	1.610s	217.345us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	0.890s	47.265us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	0.950s	44.664us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	7.020s	1.874ms	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	7.020s	1.874ms	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	7.020s	1.874ms	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	7.020s	1.874ms	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	0.950s	44.664us	1	1	100.00
		edn_sec_cm	7.020s	1.874ms	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	0.950s	44.664us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	1.610s	217.345us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	39.230s	9.003ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00