ENTROPY_SRC/RNG_4BITS Simulation Results

Tuesday September 02 2025 17:05:38 UTC

GitHub Revision: a14e715

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 4.000s 74.932us 1 1 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 3.000s 25.401us 1 1 100.00
V1 csr_rw entropy_src_csr_rw 3.000s 33.978us 1 1 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 5.000s 314.896us 1 1 100.00
V1 csr_aliasing entropy_src_csr_aliasing 7.000s 252.296us 1 1 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 5.000s 34.043us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 3.000s 33.978us 1 1 100.00
entropy_src_csr_aliasing 7.000s 252.296us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 firmware entropy_src_smoke 4.000s 74.932us 1 1 100.00
entropy_src_rng 1.367m 18.094ms 1 1 100.00
entropy_src_fw_ov 1.600m 20.141ms 1 1 100.00
V2 firmware_mode entropy_src_fw_ov 1.600m 20.141ms 1 1 100.00
V2 rng_mode entropy_src_rng 1.367m 18.094ms 1 1 100.00
V2 rng_max_rate entropy_src_rng_max_rate 4.917m 17.077ms 1 1 100.00
V2 health_checks entropy_src_rng 1.367m 18.094ms 1 1 100.00
V2 conditioning entropy_src_rng 1.367m 18.094ms 1 1 100.00
V2 interrupts entropy_src_rng 1.367m 18.094ms 1 1 100.00
entropy_src_intr 5.000s 100.001us 1 1 100.00
V2 alerts entropy_src_rng 1.367m 18.094ms 1 1 100.00
entropy_src_functional_alerts 7.000s 186.048us 1 1 100.00
V2 stress_all entropy_src_stress_all 4.583m 16.147ms 1 1 100.00
V2 functional_errors entropy_src_functional_errors 5.000s 49.317us 1 1 100.00
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 5.000s 137.265us 1 1 100.00
V2 intr_test entropy_src_intr_test 4.000s 52.365us 1 1 100.00
V2 alert_test entropy_src_alert_test 3.000s 19.690us 1 1 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 5.000s 59.346us 1 1 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 5.000s 59.346us 1 1 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 3.000s 25.401us 1 1 100.00
entropy_src_csr_rw 3.000s 33.978us 1 1 100.00
entropy_src_csr_aliasing 7.000s 252.296us 1 1 100.00
entropy_src_same_csr_outstanding 3.000s 192.451us 1 1 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 3.000s 25.401us 1 1 100.00
entropy_src_csr_rw 3.000s 33.978us 1 1 100.00
entropy_src_csr_aliasing 7.000s 252.296us 1 1 100.00
entropy_src_same_csr_outstanding 3.000s 192.451us 1 1 100.00
V2 TOTAL 12 12 100.00
V2S tl_intg_err entropy_src_sec_cm 5.000s 171.169us 1 1 100.00
entropy_src_tl_intg_err 5.000s 67.031us 1 1 100.00
V2S sec_cm_config_regwen entropy_src_rng 1.367m 18.094ms 1 1 100.00
entropy_src_cfg_regwen 5.000s 127.484us 1 1 100.00
V2S sec_cm_config_mubi entropy_src_rng 1.367m 18.094ms 1 1 100.00
V2S sec_cm_config_redun entropy_src_rng 1.367m 18.094ms 1 1 100.00
V2S sec_cm_intersig_mubi entropy_src_rng 1.367m 18.094ms 1 1 100.00
entropy_src_fw_ov 1.600m 20.141ms 1 1 100.00
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 5.000s 49.317us 1 1 100.00
entropy_src_sec_cm 5.000s 171.169us 1 1 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 5.000s 49.317us 1 1 100.00
entropy_src_sec_cm 5.000s 171.169us 1 1 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 1.367m 18.094ms 1 1 100.00
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 5.000s 49.317us 1 1 100.00
entropy_src_sec_cm 5.000s 171.169us 1 1 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 5.000s 49.317us 1 1 100.00
entropy_src_sec_cm 5.000s 171.169us 1 1 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 5.000s 49.317us 1 1 100.00
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 7.000s 186.048us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 5.000s 67.031us 1 1 100.00
V2S TOTAL 3 3 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 47.000s 9.214ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 22 22 100.00