HMAC Simulation Results

Tuesday September 02 2025 17:05:38 UTC

GitHub Revision: a14e715

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 8.770s 1.094ms 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.090s 33.659us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.060s 107.199us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 11.590s 1.114ms 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 4.660s 318.539us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 1.350s 45.929us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.060s 107.199us 1 1 100.00
hmac_csr_aliasing 4.660s 318.539us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 40.540s 6.217ms 1 1 100.00
V2 back_pressure hmac_back_pressure 49.800s 1.951ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 8.550s 351.893us 1 1 100.00
hmac_test_sha384_vectors 6.318m 33.231ms 1 1 100.00
hmac_test_sha512_vectors 6.789m 46.058ms 1 1 100.00
hmac_test_hmac256_vectors 9.510s 1.066ms 1 1 100.00
hmac_test_hmac384_vectors 11.000s 263.170us 1 1 100.00
hmac_test_hmac512_vectors 11.190s 1.275ms 1 1 100.00
V2 burst_wr hmac_burst_wr 18.600s 4.545ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 1.033m 1.351ms 1 1 100.00
V2 error hmac_error 1.183m 7.785ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 14.460s 1.400ms 1 1 100.00
V2 save_and_restore hmac_smoke 8.770s 1.094ms 1 1 100.00
hmac_long_msg 40.540s 6.217ms 1 1 100.00
hmac_back_pressure 49.800s 1.951ms 1 1 100.00
hmac_datapath_stress 1.033m 1.351ms 1 1 100.00
hmac_burst_wr 18.600s 4.545ms 1 1 100.00
hmac_stress_all 15.985m 45.998ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 8.770s 1.094ms 1 1 100.00
hmac_long_msg 40.540s 6.217ms 1 1 100.00
hmac_back_pressure 49.800s 1.951ms 1 1 100.00
hmac_datapath_stress 1.033m 1.351ms 1 1 100.00
hmac_wipe_secret 14.460s 1.400ms 1 1 100.00
hmac_test_sha256_vectors 8.550s 351.893us 1 1 100.00
hmac_test_sha384_vectors 6.318m 33.231ms 1 1 100.00
hmac_test_sha512_vectors 6.789m 46.058ms 1 1 100.00
hmac_test_hmac256_vectors 9.510s 1.066ms 1 1 100.00
hmac_test_hmac384_vectors 11.000s 263.170us 1 1 100.00
hmac_test_hmac512_vectors 11.190s 1.275ms 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 8.770s 1.094ms 1 1 100.00
hmac_long_msg 40.540s 6.217ms 1 1 100.00
hmac_back_pressure 49.800s 1.951ms 1 1 100.00
hmac_datapath_stress 1.033m 1.351ms 1 1 100.00
hmac_burst_wr 18.600s 4.545ms 1 1 100.00
hmac_error 1.183m 7.785ms 1 1 100.00
hmac_wipe_secret 14.460s 1.400ms 1 1 100.00
hmac_test_sha256_vectors 8.550s 351.893us 1 1 100.00
hmac_test_sha384_vectors 6.318m 33.231ms 1 1 100.00
hmac_test_sha512_vectors 6.789m 46.058ms 1 1 100.00
hmac_test_hmac256_vectors 9.510s 1.066ms 1 1 100.00
hmac_test_hmac384_vectors 11.000s 263.170us 1 1 100.00
hmac_test_hmac512_vectors 11.190s 1.275ms 1 1 100.00
hmac_stress_all 15.985m 45.998ms 1 1 100.00
V2 stress_all hmac_stress_all 15.985m 45.998ms 1 1 100.00
V2 alert_test hmac_alert_test 0.660s 39.328us 1 1 100.00
V2 intr_test hmac_intr_test 0.610s 19.637us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.130s 82.220us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.130s 82.220us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.090s 33.659us 1 1 100.00
hmac_csr_rw 1.060s 107.199us 1 1 100.00
hmac_csr_aliasing 4.660s 318.539us 1 1 100.00
hmac_same_csr_outstanding 1.090s 92.700us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.090s 33.659us 1 1 100.00
hmac_csr_rw 1.060s 107.199us 1 1 100.00
hmac_csr_aliasing 4.660s 318.539us 1 1 100.00
hmac_same_csr_outstanding 1.090s 92.700us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.090s 925.565us 1 1 100.00
hmac_tl_intg_err 1.650s 116.304us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 1.650s 116.304us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 8.770s 1.094ms 1 1 100.00
V3 stress_reset hmac_stress_reset 2.730s 105.955us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 3.380m 6.756ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 0.760s 110.386us 1 1 100.00
TOTAL 28 28 100.00