I2C Simulation Results

Tuesday September 02 2025 17:05:38 UTC

GitHub Revision: a14e715

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	13.960s	6.049ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	4.790s	8.612ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.690s	20.387us	1	1	100.00
V1	csr_rw	i2c_csr_rw	0.640s	104.428us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	3.050s	473.794us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.050s	54.758us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.010s	109.220us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.640s	104.428us	1	1	100.00
		i2c_csr_aliasing	1.050s	54.758us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	0.990s	43.131us	0	1	0.00
V2	host_stress_all	i2c_host_stress_all	15.661m	21.919ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	1.112m	2.496ms	1	1	100.00
V2	host_override	i2c_host_override	0.660s	24.318us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	1.675m	14.719ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	35.280s	22.437ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	0.720s	150.872us	1	1	100.00
		i2c_host_fifo_fmt_empty	12.430s	393.289us	1	1	100.00
		i2c_host_fifo_reset_rx	2.820s	755.191us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	26.860s	1.756ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	11.850s	8.726ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	0.640s	31.128us	0	1	0.00
V2	target_glitch	i2c_target_glitch	1.740s	480.974us	0	1	0.00
V2	target_stress_all	i2c_target_stress_all	41.430s	135.337ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	2.660s	1.044ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	11.200s	913.081us	1	1	100.00
		i2c_target_intr_smoke	4.110s	4.608ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	0.800s	588.088us	1	1	100.00
		i2c_target_fifo_reset_tx	0.840s	265.545us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	8.768m	52.693ms	1	1	100.00
		i2c_target_stress_rd	11.200s	913.081us	1	1	100.00
		i2c_target_intr_stress_wr	20.150s	12.144ms	0	1	0.00
V2	target_timeout	i2c_target_timeout	3.580s	1.175ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	1.220s	1.329ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	4.400s	1.638ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	3.360s	10.146ms	0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	1.650s	386.009us	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.070s	116.666us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	1.112m	2.496ms	1	1	100.00
		i2c_host_perf_precise	38.720s	5.897ms	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	11.850s	8.726ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	0.800s	25.544us	0	1	0.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	1.770s	509.180us	1	1	100.00
		i2c_target_nack_acqfull_addr	1.460s	443.785us	1	1	100.00
		i2c_target_nack_txstretch	1.000s	141.645us	0	1	0.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	3.890s	741.625us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	1.560s	2.078ms	1	1	100.00
V2	alert_test	i2c_alert_test	0.600s	17.259us	1	1	100.00
V2	intr_test	i2c_intr_test	0.640s	28.101us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	1.340s	184.717us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	1.340s	184.717us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.690s	20.387us	1	1	100.00
		i2c_csr_rw	0.640s	104.428us	1	1	100.00
		i2c_csr_aliasing	1.050s	54.758us	1	1	100.00
		i2c_same_csr_outstanding	0.880s	66.460us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.690s	20.387us	1	1	100.00
		i2c_csr_rw	0.640s	104.428us	1	1	100.00
		i2c_csr_aliasing	1.050s	54.758us	1	1	100.00
		i2c_same_csr_outstanding	0.880s	66.460us	1	1	100.00
V2		TOTAL			30	38	78.95
V2S	tl_intg_err	i2c_tl_intg_err	1.210s	246.651us	1	1	100.00
		i2c_sec_cm	0.790s	364.254us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.210s	246.651us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	9.990s	2.606ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	0.990s	485.248us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	1.390s	25.738us	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			39	50	78.00

Failure Buckets

• UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 4 failures:

  • Test i2c_host_error_intr has 1 failures.

    • 0.i2c_host_error_intr.23997957935249440020980473117995723892276285299945700289316216416653052326261
      Line 107, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

        UVM_ERROR @  43130760 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @  43130760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_host_stress_all has 1 failures.

    • 0.i2c_host_stress_all.41499782076033613575093549670600041366311416803046473731958508336152358002265
      Line 145, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

        UVM_ERROR @ 21919468659 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @ 21919468659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.52759935278273919066175855560291301458175611629595903752747012925298131060028
      Line 101, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  25738230 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @  25738230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_host_mode_toggle has 1 failures.

    • 0.i2c_host_mode_toggle.106169874038871860723418608529151496865022572280698208509602733785422447444413
      Line 78, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

        UVM_ERROR @  31128402 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @  31128402 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_target_glitch has 1 failures.

    • 0.i2c_target_glitch.63717397826159406324618048756241864627319301042652308407218669843706691953050
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

        UVM_ERROR @ 480974022 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
        UVM_INFO @ 480974022 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred! has 1 failures:

  • Test i2c_target_intr_stress_wr has 1 failures.

    • 0.i2c_target_intr_stress_wr.96913381107173490862878525017484243974365454796970248346411026858953871202451
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_intr_stress_wr/latest/run.log

        UVM_FATAL @ 12143721283 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
        UVM_INFO @ 12143721283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.51722016872955310083831763730165849675166730657915540214918540373598528849460
      Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

            Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
        UVM_ERROR @ 485248437 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
        UVM_INFO @ 485248437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:

  • Test i2c_target_hrst has 1 failures.

    • 0.i2c_target_hrst.73886853054137978088837967310797140081796684035726693764815061405195373959902
      Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log

        UVM_FATAL @ 10145839859 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
        UVM_INFO @ 10145839859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:945) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.8919696978907371077880642154978448300161678939909644796928701995257876943549
      Line 84, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2605994868 ps: (cip_base_vseq.sv:945) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2605994868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:

  • Test i2c_target_tx_stretch_ctrl has 1 failures.

    • 0.i2c_target_tx_stretch_ctrl.55171442840032583421800194742636857612798890606409728300559378992859995098946
      Line 121, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_tx_stretch_ctrl/latest/run.log

        Error-[CNST-CIF] Constraints inconsistency failure
        src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
          Constraints are inconsistent and cannot be solved.
          Please check the inconsistent constraints being printed above and rewrite
          them.
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 1 failures:

  • Test i2c_target_nack_txstretch has 1 failures.

    • 0.i2c_target_nack_txstretch.114009814005253506527707060380763526948138776698190357788857845913668753620356
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log

        UVM_ERROR @ 141644785 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
        UVM_INFO @ 141644785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---