| V1 |
smoke |
kmac_smoke |
15.890s |
1.976ms |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
kmac_csr_hw_reset |
0.780s |
47.180us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
kmac_csr_rw |
0.880s |
15.514us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
kmac_csr_bit_bash |
14.330s |
4.023ms |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
kmac_csr_aliasing |
7.080s |
4.229ms |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
kmac_csr_mem_rw_with_rand_reset |
1.230s |
109.787us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
kmac_csr_rw |
0.880s |
15.514us |
1 |
1 |
100.00 |
|
|
kmac_csr_aliasing |
7.080s |
4.229ms |
1 |
1 |
100.00 |
| V1 |
mem_walk |
kmac_mem_walk |
0.690s |
85.388us |
1 |
1 |
100.00 |
| V1 |
mem_partial_access |
kmac_mem_partial_access |
1.140s |
66.948us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
8 |
8 |
100.00 |
| V2 |
long_msg_and_output |
kmac_long_msg_and_output |
40.250m |
170.030ms |
1 |
1 |
100.00 |
| V2 |
burst_write |
kmac_burst_write |
15.109m |
31.883ms |
1 |
1 |
100.00 |
| V2 |
test_vectors |
kmac_test_vectors_sha3_224 |
37.030s |
10.448ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_sha3_256 |
30.024m |
114.447ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_sha3_384 |
22.652m |
45.773ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_sha3_512 |
13.130s |
3.618ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_shake_128 |
38.924m |
377.814ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_shake_256 |
29.623m |
60.132ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_kmac |
2.230s |
45.771us |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_kmac_xof |
3.830s |
309.771us |
1 |
1 |
100.00 |
| V2 |
sideload |
kmac_sideload |
56.960s |
1.124ms |
1 |
1 |
100.00 |
| V2 |
app |
kmac_app |
1.062m |
3.862ms |
1 |
1 |
100.00 |
| V2 |
app_with_partial_data |
kmac_app_with_partial_data |
1.115m |
9.283ms |
1 |
1 |
100.00 |
| V2 |
entropy_refresh |
kmac_entropy_refresh |
2.823m |
5.838ms |
1 |
1 |
100.00 |
| V2 |
error |
kmac_error |
34.050s |
4.912ms |
1 |
1 |
100.00 |
| V2 |
key_error |
kmac_key_error |
3.870s |
493.574us |
1 |
1 |
100.00 |
| V2 |
sideload_invalid |
kmac_sideload_invalid |
3.560s |
439.435us |
1 |
1 |
100.00 |
| V2 |
edn_timeout_error |
kmac_edn_timeout_error |
13.330s |
592.443us |
1 |
1 |
100.00 |
| V2 |
entropy_mode_error |
kmac_entropy_mode_error |
1.060s |
16.436us |
1 |
1 |
100.00 |
| V2 |
entropy_ready_error |
kmac_entropy_ready_error |
21.780s |
5.856ms |
1 |
1 |
100.00 |
| V2 |
lc_escalation |
kmac_lc_escalation |
1.550s |
103.697us |
1 |
1 |
100.00 |
| V2 |
stress_all |
kmac_stress_all |
17.640m |
116.241ms |
1 |
1 |
100.00 |
| V2 |
intr_test |
kmac_intr_test |
0.750s |
26.489us |
1 |
1 |
100.00 |
| V2 |
alert_test |
kmac_alert_test |
0.960s |
32.984us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
kmac_tl_errors |
1.310s |
174.954us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
kmac_tl_errors |
1.310s |
174.954us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
kmac_csr_hw_reset |
0.780s |
47.180us |
1 |
1 |
100.00 |
|
|
kmac_csr_rw |
0.880s |
15.514us |
1 |
1 |
100.00 |
|
|
kmac_csr_aliasing |
7.080s |
4.229ms |
1 |
1 |
100.00 |
|
|
kmac_same_csr_outstanding |
2.080s |
104.408us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
kmac_csr_hw_reset |
0.780s |
47.180us |
1 |
1 |
100.00 |
|
|
kmac_csr_rw |
0.880s |
15.514us |
1 |
1 |
100.00 |
|
|
kmac_csr_aliasing |
7.080s |
4.229ms |
1 |
1 |
100.00 |
|
|
kmac_same_csr_outstanding |
2.080s |
104.408us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
26 |
26 |
100.00 |
| V2S |
shadow_reg_update_error |
kmac_shadow_reg_errors |
1.860s |
134.670us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_read_clear_staged_value |
kmac_shadow_reg_errors |
1.860s |
134.670us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_storage_error |
kmac_shadow_reg_errors |
1.860s |
134.670us |
1 |
1 |
100.00 |
| V2S |
shadowed_reset_glitch |
kmac_shadow_reg_errors |
1.860s |
134.670us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error_with_csr_rw |
kmac_shadow_reg_errors_with_csr_rw |
3.110s |
87.353us |
1 |
1 |
100.00 |
| V2S |
tl_intg_err |
kmac_sec_cm |
1.341m |
30.168ms |
1 |
1 |
100.00 |
|
|
kmac_tl_intg_err |
1.910s |
83.340us |
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
kmac_tl_intg_err |
1.910s |
83.340us |
1 |
1 |
100.00 |
| V2S |
sec_cm_lc_escalate_en_intersig_mubi |
kmac_lc_escalation |
1.550s |
103.697us |
1 |
1 |
100.00 |
| V2S |
sec_cm_sw_key_key_masking |
kmac_smoke |
15.890s |
1.976ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_key_sideload |
kmac_sideload |
56.960s |
1.124ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_cfg_shadowed_config_shadow |
kmac_shadow_reg_errors |
1.860s |
134.670us |
1 |
1 |
100.00 |
| V2S |
sec_cm_fsm_sparse |
kmac_sec_cm |
1.341m |
30.168ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_ctr_redun |
kmac_sec_cm |
1.341m |
30.168ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_packer_ctr_redun |
kmac_sec_cm |
1.341m |
30.168ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_cfg_shadowed_config_regwen |
kmac_smoke |
15.890s |
1.976ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_fsm_global_esc |
kmac_lc_escalation |
1.550s |
103.697us |
1 |
1 |
100.00 |
| V2S |
sec_cm_fsm_local_esc |
kmac_sec_cm |
1.341m |
30.168ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_absorbed_ctrl_mubi |
kmac_mubi |
1.258m |
6.409ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_sw_cmd_ctrl_sparse |
kmac_smoke |
15.890s |
1.976ms |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
5 |
5 |
100.00 |
| V3 |
stress_all_with_rand_reset |
kmac_stress_all_with_rand_reset |
1.247m |
4.112ms |
1 |
1 |
100.00 |
| V3 |
|
TOTAL |
|
|
1 |
1 |
100.00 |
|
|
TOTAL |
|
|
40 |
40 |
100.00 |