PATTGEN Simulation Results

Tuesday September 02 2025 17:05:38 UTC

GitHub Revision: a14e715

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	3.000s	113.890us	1	1	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	2.000s	30.034us	1	1	100.00
V1	csr_rw	pattgen_csr_rw	3.000s	13.983us	1	1	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	3.000s	38.756us	1	1	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	19.032us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	3.000s	78.004us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	3.000s	13.983us	1	1	100.00
		pattgen_csr_aliasing	3.000s	19.032us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	perf	pattgen_perf	2.783m	24.795ms	1	1	100.00
V2	cnt_rollover	cnt_rollover	34.000s	5.019ms	1	1	100.00
V2	error	pattgen_error	3.000s	65.302us	1	1	100.00
V2	stress_all	pattgen_stress_all			0	1	0.00
V2	alert_test	pattgen_alert_test	3.000s	15.359us	1	1	100.00
V2	intr_test	pattgen_intr_test	2.000s	95.192us	1	1	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	4.000s	92.976us	1	1	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	4.000s	92.976us	1	1	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	2.000s	30.034us	1	1	100.00
		pattgen_csr_rw	3.000s	13.983us	1	1	100.00
		pattgen_csr_aliasing	3.000s	19.032us	1	1	100.00
		pattgen_same_csr_outstanding	3.000s	32.437us	1	1	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	2.000s	30.034us	1	1	100.00
		pattgen_csr_rw	3.000s	13.983us	1	1	100.00
		pattgen_csr_aliasing	3.000s	19.032us	1	1	100.00
		pattgen_same_csr_outstanding	3.000s	32.437us	1	1	100.00
V2		TOTAL			7	8	87.50
V2S	tl_intg_err	pattgen_tl_intg_err	4.000s	75.274us	1	1	100.00
		pattgen_sec_cm	3.000s	68.527us	1	1	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	4.000s	75.274us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	25.000s	2.661ms	0	1	0.00
V3		TOTAL			0	1	0.00
	Unmapped tests	pattgen_inactive_level	5.000s	1.165ms	1	1	100.00
		TOTAL			16	18	88.89

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:946) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test pattgen_stress_all_with_rand_reset has 1 failures.

    • 0.pattgen_stress_all_with_rand_reset.18833742575839808054090490358257726106570083823941281945844529356015073887240
      Line 116, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1110852411 ps: (cip_base_vseq.sv:946) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_ERROR @ 1110859415 ps: (cip_base_vseq.sv:850) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 1110859415 ps: (cip_base_vseq.sv:853) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
        Issuing reset for run 1/5
        UVM_INFO @ 1110954149 ps: (cip_base_vseq.sv:874) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
      

• Job timed out after * minutes has 1 failures:

  • Test pattgen_stress_all has 1 failures.

    • 0.pattgen_stress_all.77675787230836218774453864546205376105260326529276921260640177770634927906101
      Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all/latest/run.log

        Job timed out after 180 minutes