RV_DM/USE_JTAG_INTERFACE Simulation Results

Tuesday September 02 2025 17:05:38 UTC

GitHub Revision: `a14e715`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rv_dm_smoke	12.160s	12.570ms	0	1	0.00
V1	jtag_dtm_csr_hw_reset	rv_dm_jtag_dtm_csr_hw_reset	1.310s	552.152us	1	1	100.00
V1	jtag_dtm_csr_rw	rv_dm_jtag_dtm_csr_rw	1.070s	476.178us	1	1	100.00
V1	jtag_dtm_csr_bit_bash	rv_dm_jtag_dtm_csr_bit_bash	5.310s	6.649ms	1	1	100.00
V1	jtag_dtm_csr_aliasing	rv_dm_jtag_dtm_csr_aliasing	1.160s	539.493us	1	1	100.00
V1	jtag_dmi_csr_hw_reset	rv_dm_jtag_dmi_csr_hw_reset	3.540s	5.224ms	1	1	100.00
V1	jtag_dmi_csr_rw	rv_dm_jtag_dmi_csr_rw	2.560s	1.356ms	1	1	100.00
V1	jtag_dmi_csr_bit_bash	rv_dm_jtag_dmi_csr_bit_bash	15.870s	12.927ms	1	1	100.00
V1	jtag_dmi_csr_aliasing	rv_dm_jtag_dmi_csr_aliasing	40.540s	19.950ms	1	1	100.00
V1	jtag_dmi_cmderr_busy	rv_dm_cmderr_busy	1.010s	390.708us	1	1	100.00
V1	jtag_dmi_cmderr_not_supported	rv_dm_cmderr_not_supported	1.040s	195.348us	1	1	100.00
V1	cmderr_exception	rv_dm_cmderr_exception	1.070s	227.409us	1	1	100.00
V1	mem_tl_access_resuming	rv_dm_mem_tl_access_resuming	0.900s	653.505us	1	1	100.00
V1	mem_tl_access_halted	rv_dm_mem_tl_access_halted	1.250s	503.855us	1	1	100.00
V1	cmderr_halt_resume	rv_dm_cmderr_halt_resume	3.130s	1.357ms	1	1	100.00
V1	dataaddr_rw_access	rv_dm_dataaddr_rw_access	0.830s	87.577us	1	1	100.00
V1	halt_resume	rv_dm_halt_resume_whereto	1.040s	188.687us	1	1	100.00
V1	progbuf_busy	rv_dm_cmderr_busy	1.010s	390.708us	1	1	100.00
V1	abstractcmd_status	rv_dm_abstractcmd_status	0.890s	224.274us	1	1	100.00
V1	progbuf_read_write_execute	rv_dm_progbuf_read_write_execute	1.210s	255.912us	1	1	100.00
V1	progbuf_exception	rv_dm_cmderr_exception	1.070s	227.409us	1	1	100.00
V1	rom_read_access	rv_dm_rom_read_access	0.860s	163.378us	1	1	100.00
V1	csr_hw_reset	rv_dm_csr_hw_reset	2.120s	380.644us	1	1	100.00
V1	csr_rw	rv_dm_csr_rw	1.490s	74.276us	1	1	100.00
V1	csr_bit_bash	rv_dm_csr_bit_bash	37.560s	1.504ms	1	1	100.00
V1	csr_aliasing	rv_dm_csr_aliasing	44.190s	1.137ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_dm_csr_mem_rw_with_rand_reset	0.760s	53.593us	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_dm_csr_aliasing	44.190s	1.137ms	1	1	100.00
		rv_dm_csr_rw	1.490s	74.276us	1	1	100.00
V1	mem_walk	rv_dm_mem_walk	0.970s	146.907us	1	1	100.00
V1	mem_partial_access	rv_dm_mem_partial_access	1.120s	105.367us	1	1	100.00
V1		TOTAL			25	27	92.59
V2	idcode	rv_dm_smoke	12.160s	12.570ms	0	1	0.00
V2	jtag_dtm_hard_reset	rv_dm_jtag_dtm_hard_reset	0.860s	168.551us	1	1	100.00
V2	jtag_dtm_idle_hint	rv_dm_jtag_dtm_idle_hint	0.860s	664.684us	1	1	100.00
V2	jtag_dmi_failed_op	rv_dm_dmi_failed_op	1.770s	433.711us	1	1	100.00
V2	jtag_dmi_dm_inactive	rv_dm_jtag_dmi_dm_inactive	5.200s	2.482ms	1	1	100.00
V2	sba	rv_dm_sba_tl_access	1.318m	300.000ms	0	1	0.00
		rv_dm_delayed_resp_sba_tl_access	2.926m	300.000ms	0	1	0.00
V2	bad_sba	rv_dm_bad_sba_tl_access	3.207m	300.000ms	0	1	0.00
V2	sba_autoincrement	rv_dm_autoincr_sba_tl_access	9.274m	300.000ms	0	1	0.00
V2	jtag_dmi_debug_disabled	rv_dm_jtag_dmi_debug_disabled	1.080s	284.161us	1	1	100.00
V2	sba_debug_disabled	rv_dm_sba_debug_disabled	7.540s	3.697ms	1	1	100.00
V2	ndmreset_req	rv_dm_ndmreset_req	1.000s	145.220us	1	1	100.00
V2	hart_unavail	rv_dm_hart_unavail	0.850s	132.374us	1	1	100.00
V2	tap_ctrl_transitions	rv_dm_tap_fsm	25.120s	12.027ms	0	1	0.00
		rv_dm_tap_fsm_rand_reset	1.070s	21.181us	0	1	0.00
V2	hartsel_warl	rv_dm_hartsel_warl	0.850s	110.773us	1	1	100.00
V2	stress_all	rv_dm_stress_all	1.080s	1.686ms	1	1	100.00
V2	alert_test	rv_dm_alert_test	0.700s	146.362us	1	1	100.00
V2	tl_d_oob_addr_access	rv_dm_tl_errors	3.270s	170.316us	1	1	100.00
V2	tl_d_illegal_access	rv_dm_tl_errors	3.270s	170.316us	1	1	100.00
V2	tl_d_outstanding_access	rv_dm_csr_aliasing	44.190s	1.137ms	1	1	100.00
		rv_dm_csr_hw_reset	2.120s	380.644us	1	1	100.00
		rv_dm_csr_rw	1.490s	74.276us	1	1	100.00
		rv_dm_same_csr_outstanding	3.500s	1.190ms	1	1	100.00
V2	tl_d_partial_access	rv_dm_csr_aliasing	44.190s	1.137ms	1	1	100.00
		rv_dm_csr_hw_reset	2.120s	380.644us	1	1	100.00
		rv_dm_csr_rw	1.490s	74.276us	1	1	100.00
		rv_dm_same_csr_outstanding	3.500s	1.190ms	1	1	100.00
V2		TOTAL			13	19	68.42
V2S	tl_intg_err	rv_dm_sec_cm	1.640s	1.158ms	1	1	100.00
		rv_dm_tl_intg_err	15.550s	2.626ms	1	1	100.00
V2S	sec_cm_bus_integrity	rv_dm_tl_intg_err	15.550s	2.626ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	rv_dm_sba_debug_disabled	7.540s	3.697ms	1	1	100.00
		rv_dm_debug_disabled	0.860s	87.902us	1	1	100.00
V2S	sec_cm_lc_dft_en_intersig_mubi	rv_dm_sba_debug_disabled	7.540s	3.697ms	1	1	100.00
		rv_dm_debug_disabled	0.860s	87.902us	1	1	100.00
V2S	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi	rv_dm_smoke	12.160s	12.570ms	0	1	0.00
V2S	sec_cm_dm_en_ctrl_lc_gated	rv_dm_buffered_enable	0.910s	111.185us	1	1	100.00
V2S	sec_cm_sba_tl_lc_gate_fsm_sparse	rv_dm_sparse_lc_gate_fsm	0.970s	97.047us	1	1	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	rv_dm_sparse_lc_gate_fsm	0.970s	97.047us	1	1	100.00
V2S	sec_cm_exec_ctrl_mubi	rv_dm_buffered_enable	0.910s	111.185us	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	rv_dm_stress_all_with_rand_reset	1.040s	67.737us	0	1	0.00
V3		TOTAL			0	1	0.00
	Unmapped tests	rv_dm_scanmode	0.610s	30.973us	1	1	100.00
		TOTAL			44	53	83.02

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:
- Test rv_dm_sba_tl_access has 1 failures.
  - 0.rv_dm_sba_tl_access.23417269760645323700204378322858234662535680768308063372937447408815306881384
    Line 83, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_sba_tl_access/latest/run.log
```
  UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rv_dm_delayed_resp_sba_tl_access has 1 failures.
  - 0.rv_dm_delayed_resp_sba_tl_access.87147642633963980757558313616061631881311143261468216994164779985018687136087
    Line 83, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_delayed_resp_sba_tl_access/latest/run.log
```
  UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rv_dm_bad_sba_tl_access has 1 failures.
  - 0.rv_dm_bad_sba_tl_access.3279534579951033077010252415941844012649914160119945553887223429540120981593
    Line 83, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_bad_sba_tl_access/latest/run.log
```
  UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rv_dm_autoincr_sba_tl_access has 1 failures.
  - 0.rv_dm_autoincr_sba_tl_access.67262073717889691307160601652457025562397352411262926162641541893820152613891
    Line 83, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_autoincr_sba_tl_access/latest/run.log
```
  UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Error-[NOA] Null object access has 2 failures:

Test rv_dm_smoke has 1 failures.

0.rv_dm_smoke.87157504824025184744663193659822476431517989000774872657202558514982356969405
Line 78, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_smoke/latest/run.log

  Error-[NOA] Null object access
  src/lowrisc_dv_cip_lib_0/seq_lib/cip_base_vseq.sv, 290
    The object at dereference depth 0 is being used before it was
    constructed/allocated.
    Please make sure that the object is allocated before using it.

Test rv_dm_tap_fsm has 1 failures.

0.rv_dm_tap_fsm.32620179108888296470382537946920596283994658582180467301936421950598903797918
Line 94, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_tap_fsm/latest/run.log

  Error-[NOA] Null object access
  src/lowrisc_dv_cip_lib_0/seq_lib/cip_base_vseq.sv, 304
    The object at dereference depth 0 is being used before it was
    constructed/allocated.
    Please make sure that the object is allocated before using it.

UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@6761) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test rv_dm_tap_fsm_rand_reset has 1 failures.

0.rv_dm_tap_fsm_rand_reset.25965510004735762274599120723456872372819215068097024013800011372936947215778
Line 76, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_tap_fsm_rand_reset/latest/run.log

  UVM_ERROR @  21180802 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@6761) { a_addr: 'hb82e06dc  a_data: 'hcc37537a  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h52  a_opcode: 'h4  a_user: 'h19bd4  d_param: 'h0  d_source: 'h52  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @  21180802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@13747) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test rv_dm_stress_all_with_rand_reset has 1 failures.

0.rv_dm_stress_all_with_rand_reset.2761219379178926901867553617051863443247565091346600489943398595878890812674
Line 82, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  67736727 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@13747) { a_addr: 'h2044a464  a_data: 'h9a125434  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hb4  a_opcode: 'h4  a_user: 'h1bf90  d_param: 'h0  d_source: 'hb4  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @  67736727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@5663) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test rv_dm_csr_mem_rw_with_rand_reset has 1 failures.

0.rv_dm_csr_mem_rw_with_rand_reset.8453196006606677358951568188899813201831085446030484862962566242408208241940
Line 76, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @  53592588 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@5663) { a_addr: 'hbed497d8  a_data: 'hf80a6ed1  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h78  a_opcode: 'h4  a_user: 'h19f02  d_param: 'h0  d_source: 'h78  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @  53592588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---