SPI_HOST Simulation Results

Tuesday September 02 2025 17:05:38 UTC

GitHub Revision: a14e715

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	6.000s	327.775us	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	3.000s	40.280us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	2.000s	14.755us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	4.000s	58.447us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	3.000s	30.632us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	3.000s	26.606us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	2.000s	14.755us	1	1	100.00
		spi_host_csr_aliasing	3.000s	30.632us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	3.000s	20.966us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	3.000s	69.464us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	3.000s	23.221us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	4.000s	130.021us	1	1	100.00
		spi_host_error_cmd	2.000s	16.426us	1	1	100.00
		spi_host_event	8.000s	285.519us	1	1	100.00
V2	clock_rate	spi_host_speed	3.000s	84.915us	1	1	100.00
V2	speed	spi_host_speed	3.000s	84.915us	1	1	100.00
V2	chip_select_timing	spi_host_speed	3.000s	84.915us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	4.000s	63.497us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	3.000s	27.982us	1	1	100.00
V2	cpol_cpha	spi_host_speed	3.000s	84.915us	1	1	100.00
V2	full_cycle	spi_host_speed	3.000s	84.915us	1	1	100.00
V2	duplex	spi_host_smoke	6.000s	327.775us	1	1	100.00
V2	tx_rx_only	spi_host_smoke	6.000s	327.775us	1	1	100.00
V2	stress_all	spi_host_stress_all	4.000s	186.074us	1	1	100.00
V2	spien	spi_host_spien	4.000s	300.592us	1	1	100.00
V2	stall	spi_host_status_stall	31.000s	7.577ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	4.000s	427.526us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	4.000s	130.021us	1	1	100.00
V2	alert_test	spi_host_alert_test	3.000s	36.735us	1	1	100.00
V2	intr_test	spi_host_intr_test	3.000s	20.574us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	4.000s	171.338us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	4.000s	171.338us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	3.000s	40.280us	1	1	100.00
		spi_host_csr_rw	2.000s	14.755us	1	1	100.00
		spi_host_csr_aliasing	3.000s	30.632us	1	1	100.00
		spi_host_same_csr_outstanding	3.000s	91.172us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	3.000s	40.280us	1	1	100.00
		spi_host_csr_rw	2.000s	14.755us	1	1	100.00
		spi_host_csr_aliasing	3.000s	30.632us	1	1	100.00
		spi_host_same_csr_outstanding	3.000s	91.172us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	3.000s	132.512us	1	1	100.00
		spi_host_sec_cm	3.000s	151.516us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	3.000s	132.512us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	5.333m	200.000ms	0	1	0.00
		TOTAL			25	26	96.15

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test spi_host_upper_range_clkdiv has 1 failures.

    • 0.spi_host_upper_range_clkdiv.41020628391223832472741920868553117803963710399225832686220974906296243034138
      Line 124, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/0.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---