SYSRST_CTRL Simulation Results

Tuesday September 02 2025 17:05:38 UTC

GitHub Revision: a14e715

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sysrst_ctrl_smoke 2.360s 2.122ms 1 1 100.00
V1 input_output_inverted sysrst_ctrl_in_out_inverted 1.830s 2.472ms 1 1 100.00
V1 combo_detect_ec_rst sysrst_ctrl_combo_detect_ec_rst 4.920s 2.252ms 1 1 100.00
V1 combo_detect_ec_rst_with_pre_cond sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 2.600s 2.512ms 1 1 100.00
V1 csr_hw_reset sysrst_ctrl_csr_hw_reset 11.870s 6.030ms 1 1 100.00
V1 csr_rw sysrst_ctrl_csr_rw 1.090s 2.222ms 1 1 100.00
V1 csr_bit_bash sysrst_ctrl_csr_bit_bash 24.460s 24.166ms 1 1 100.00
V1 csr_aliasing sysrst_ctrl_csr_aliasing 3.310s 2.484ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset sysrst_ctrl_csr_mem_rw_with_rand_reset 2.530s 2.093ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr sysrst_ctrl_csr_rw 1.090s 2.222ms 1 1 100.00
sysrst_ctrl_csr_aliasing 3.310s 2.484ms 1 1 100.00
V1 TOTAL 9 9 100.00
V2 combo_detect sysrst_ctrl_combo_detect 58.420s 118.324ms 1 1 100.00
V2 combo_detect_with_pre_cond sysrst_ctrl_combo_detect_with_pre_cond 2.255m 78.805ms 1 1 100.00
V2 auto_block_key_outputs sysrst_ctrl_auto_blk_key_output 1.110m 133.189ms 1 1 100.00
V2 keyboard_input_triggered_interrupt sysrst_ctrl_edge_detect 2.260s 3.275ms 1 1 100.00
V2 pin_output_keyboard_inversion_control sysrst_ctrl_pin_override_test 2.090s 2.535ms 1 1 100.00
V2 pin_input_value_accessibility sysrst_ctrl_pin_access_test 4.440s 2.124ms 1 1 100.00
V2 ec_power_on_reset sysrst_ctrl_ec_pwr_on_rst 2.640s 4.422ms 1 1 100.00
V2 flash_write_protect_output sysrst_ctrl_flash_wr_prot_out 2.780s 2.618ms 1 1 100.00
V2 ultra_low_power_test sysrst_ctrl_ultra_low_pwr 5.640s 10.796ms 1 1 100.00
V2 sysrst_ctrl_feature_disable sysrst_ctrl_feature_disable 20.830s 38.694ms 1 1 100.00
V2 stress_all sysrst_ctrl_stress_all 3.112m 424.240ms 1 1 100.00
V2 alert_test sysrst_ctrl_alert_test 4.010s 2.012ms 1 1 100.00
V2 intr_test sysrst_ctrl_intr_test 4.460s 2.013ms 1 1 100.00
V2 tl_d_oob_addr_access sysrst_ctrl_tl_errors 2.460s 2.561ms 1 1 100.00
V2 tl_d_illegal_access sysrst_ctrl_tl_errors 2.460s 2.561ms 1 1 100.00
V2 tl_d_outstanding_access sysrst_ctrl_csr_hw_reset 11.870s 6.030ms 1 1 100.00
sysrst_ctrl_csr_rw 1.090s 2.222ms 1 1 100.00
sysrst_ctrl_csr_aliasing 3.310s 2.484ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 4.210s 7.529ms 1 1 100.00
V2 tl_d_partial_access sysrst_ctrl_csr_hw_reset 11.870s 6.030ms 1 1 100.00
sysrst_ctrl_csr_rw 1.090s 2.222ms 1 1 100.00
sysrst_ctrl_csr_aliasing 3.310s 2.484ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 4.210s 7.529ms 1 1 100.00
V2 TOTAL 15 15 100.00
V2S tl_intg_err sysrst_ctrl_sec_cm 11.780s 22.070ms 1 1 100.00
sysrst_ctrl_tl_intg_err 1.225m 42.461ms 1 1 100.00
V2S sec_cm_bus_integrity sysrst_ctrl_tl_intg_err 1.225m 42.461ms 1 1 100.00
V2S TOTAL 2 2 100.00
V3 stress_all_with_rand_reset sysrst_ctrl_stress_all_with_rand_reset 5.270s 4.993ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 27 27 100.00