UART Simulation Results

Tuesday September 02 2025 17:05:38 UTC

GitHub Revision: a14e715

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	4.100s	642.257us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.590s	23.297us	1	1	100.00
V1	csr_rw	uart_csr_rw	0.550s	18.693us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.830s	514.285us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	0.750s	44.788us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	0.820s	59.650us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.550s	18.693us	1	1	100.00
		uart_csr_aliasing	0.750s	44.788us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	34.340s	31.840ms	1	1	100.00
V2	parity	uart_smoke	4.100s	642.257us	1	1	100.00
		uart_tx_rx	34.340s	31.840ms	1	1	100.00
V2	parity_error	uart_intr	13.330s	31.356ms	1	1	100.00
		uart_rx_parity_err	14.010s	46.473ms	1	1	100.00
V2	watermark	uart_tx_rx	34.340s	31.840ms	1	1	100.00
		uart_intr	13.330s	31.356ms	1	1	100.00
V2	fifo_full	uart_fifo_full	2.989m	139.252ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	26.490s	105.797ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	9.670s	39.135ms	1	1	100.00
V2	rx_frame_err	uart_intr	13.330s	31.356ms	1	1	100.00
V2	rx_break_err	uart_intr	13.330s	31.356ms	1	1	100.00
V2	rx_timeout	uart_intr	13.330s	31.356ms	1	1	100.00
V2	perf	uart_perf	1.878m	12.294ms	1	1	100.00
V2	sys_loopback	uart_loopback	3.040s	2.052ms	1	1	100.00
V2	line_loopback	uart_loopback	3.040s	2.052ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	12.650s	10.773ms	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.270s	2.519ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	2.520s	660.357us	1	1	100.00
V2	rx_oversample	uart_rx_oversample	23.890s	6.600ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	1.505m	81.170ms	1	1	100.00
V2	stress_all	uart_stress_all	4.189m	144.761ms	1	1	100.00
V2	alert_test	uart_alert_test	0.590s	62.600us	1	1	100.00
V2	intr_test	uart_intr_test	0.690s	23.359us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.440s	32.680us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.440s	32.680us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.590s	23.297us	1	1	100.00
		uart_csr_rw	0.550s	18.693us	1	1	100.00
		uart_csr_aliasing	0.750s	44.788us	1	1	100.00
		uart_same_csr_outstanding	0.710s	44.756us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.590s	23.297us	1	1	100.00
		uart_csr_rw	0.550s	18.693us	1	1	100.00
		uart_csr_aliasing	0.750s	44.788us	1	1	100.00
		uart_same_csr_outstanding	0.710s	44.756us	1	1	100.00
V2		TOTAL			17	18	94.44
V2S	tl_intg_err	uart_sec_cm	0.980s	125.382us	1	1	100.00
		uart_tl_intg_err	0.810s	196.415us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	0.810s	196.415us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	13.040s	1.606ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	27	96.30

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * has 1 failures:
  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.108580151769668470978674519733312047481364079919473085702860083942973230780099
      Line 74, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @ 7464733460 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 7464733460 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
        UVM_ERROR @ 7553298079 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
        UVM_ERROR @ 7553298079 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 7683026535 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1