CHIP Simulation Results

Tuesday September 02 2025 17:05:38 UTC

GitHub Revision: `a14e715`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	2.043m	2.436ms	1	1	100.00
		chip_sw_example_rom	1.093m	2.515ms	1	1	100.00
		chip_sw_example_manufacturer	1.566m	2.108ms	1	1	100.00
		chip_sw_example_concurrency	2.142m	2.766ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	3.468m	6.179ms	1	1	100.00
V1	csr_rw	chip_csr_rw	6.309m	5.511ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	12.812m	9.188ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	1.105h	31.268ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	54.360s	2.097ms	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	1.105h	31.268ms	1	1	100.00
		chip_csr_rw	6.309m	5.511ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	5.810s	149.166us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	5.167m	4.091ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	5.167m	4.091ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	5.167m	4.091ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	6.073m	4.382ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	6.073m	4.382ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	6.324m	4.445ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	6.014m	4.703ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	6.243m	4.142ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	6.307m	4.860ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	5.397m	4.097ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	3.894m	3.520ms	1	1	100.00
V1		TOTAL			17	18	94.44
V2	chip_pin_mux	chip_padctrl_attributes	3.233m	4.345ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	3.233m	4.345ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	3.359m	3.139ms	0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	5.094m	6.406ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	3.818m	4.827ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	10.478m	8.896ms	1	1	100.00
		chip_tap_straps_testunlock0	3.518m	4.377ms	1	1	100.00
		chip_tap_straps_rma	3.737m	4.328ms	1	1	100.00
		chip_tap_straps_prod	15.774m	14.034ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	3.169m	2.923ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	14.228m	8.127ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	6.678m	6.126ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	6.678m	6.126ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	8.796m	7.382ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	18.610m	15.284ms	1	1	100.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	6.180m	4.437ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	10.049m	6.444ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	55.716m	18.294ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.980m	2.878ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	10.263m	5.968ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.907m	3.335ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	18.490m	9.836ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.623m	3.132ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.732m	4.689ms	1	1	100.00
		chip_sw_clkmgr_jitter	1.928m	1.905ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	2.808m	3.040ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	3.588m	4.692ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.336m	5.347ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	2.501m	3.427ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.336m	5.347ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	2.425m	2.496ms	1	1	100.00
		chip_sw_aes_smoketest	2.731m	3.321ms	1	1	100.00
		chip_sw_aon_timer_smoketest	2.657m	2.930ms	1	1	100.00
		chip_sw_clkmgr_smoketest	1.639m	2.819ms	1	1	100.00
		chip_sw_csrng_smoketest	2.065m	3.015ms	1	1	100.00
		chip_sw_entropy_src_smoketest	12.962m	6.189ms	1	1	100.00
		chip_sw_gpio_smoketest	2.473m	2.687ms	1	1	100.00
		chip_sw_hmac_smoketest	2.870m	2.765ms	1	1	100.00
		chip_sw_kmac_smoketest	3.290m	2.900ms	1	1	100.00
		chip_sw_otbn_smoketest	9.133m	5.907ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	3.740m	6.341ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	4.480m	5.361ms	1	1	100.00
		chip_sw_rv_plic_smoketest	2.155m	3.068ms	1	1	100.00
		chip_sw_rv_timer_smoketest	2.609m	3.093ms	1	1	100.00
		chip_sw_rstmgr_smoketest	1.650m	2.174ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	1.624m	2.086ms	1	1	100.00
		chip_sw_uart_smoketest	2.019m	2.689ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	2.582m	2.734ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	5.317m	4.444ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	2.161h	61.196ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	41.760m	15.080ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	2.253m	4.160ms	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	3.496m	3.131ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	3.120m	3.456ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.997h	53.731ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.958h	56.998ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	50.440s	1.879ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	50.440s	1.879ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	1.105h	31.268ms	1	1	100.00
		chip_same_csr_outstanding	15.164m	14.246ms	1	1	100.00
		chip_csr_hw_reset	3.468m	6.179ms	1	1	100.00
		chip_csr_rw	6.309m	5.511ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	1.105h	31.268ms	1	1	100.00
		chip_same_csr_outstanding	15.164m	14.246ms	1	1	100.00
		chip_csr_hw_reset	3.468m	6.179ms	1	1	100.00
		chip_csr_rw	6.309m	5.511ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	40.030s	1.724ms	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	4.040s	39.306us	1	1	100.00
		xbar_smoke_large_delays	45.220s	7.360ms	1	1	100.00
		xbar_smoke_slow_rsp	46.570s	5.317ms	1	1	100.00
		xbar_random_zero_delays	15.470s	271.110us	1	1	100.00
		xbar_random_large_delays	5.357m	50.603ms	1	1	100.00
		xbar_random_slow_rsp	3.308m	21.410ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	9.890s	115.642us	1	1	100.00
		xbar_error_and_unmapped_addr	4.510s	53.632us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	27.650s	555.711us	1	1	100.00
		xbar_error_and_unmapped_addr	4.510s	53.632us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	28.470s	594.612us	1	1	100.00
		xbar_access_same_device_slow_rsp	7.436m	47.908ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	5.240s	60.810us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	2.038m	5.218ms	1	1	100.00
		xbar_stress_all_with_error	1.555m	1.763ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	7.609m	12.889ms	1	1	100.00
		xbar_stress_all_with_reset_error	7.112m	6.414ms	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	41.760m	15.080ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	36.559m	30.264ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	39.905m	14.960ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	33.242m	10.751ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	43.645m	15.507ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	42.679m	15.666ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	43.901m	15.254ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	43.263m	15.000ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	16.410s	10.140us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	16.860s	10.320us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	17.140s	10.140us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	17.330s	10.180us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	16.820s	10.100us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	17.000s	10.360us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	16.960s	10.280us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	16.500s	10.220us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	16.610s	10.380us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	17.890s	10.140us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	17.960s	10.180us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	18.180s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	17.880s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	15.970s	10.380us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	15.860s	10.320us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	18.200s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	16.340s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	17.620s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	16.180s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	16.880s	10.180us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	17.770s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	16.200s	10.380us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	16.330s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	17.180s	10.180us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	16.110s	10.280us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	32.605m	11.728ms	1	1	100.00
		rom_e2e_asm_init_dev	40.476m	15.657ms	1	1	100.00
		rom_e2e_asm_init_prod	42.296m	17.960ms	1	1	100.00
		rom_e2e_asm_init_prod_end	39.373m	16.699ms	1	1	100.00
		rom_e2e_asm_init_rma	41.098m	16.827ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	39.014m	15.384ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	37.622m	15.499ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	41.060m	18.522ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	42.056m	17.633ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	47.413m	34.617ms	0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	47.413m	34.617ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	3.263m	3.338ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.980m	2.878ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	2.096m	3.182ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	2.669m	3.010ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	25.406m	11.170ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	2.423m	2.749ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	6.163m	6.049ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	6.766m	6.072ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	9.787m	5.276ms	1	1	100.00
		chip_plic_all_irqs_10	5.237m	3.248ms	1	1	100.00
		chip_plic_all_irqs_20	5.327m	4.030ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	2.521m	3.217ms	0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	12.207m	9.559ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	3.947m	4.400ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	1.899m	3.296ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	12.995m	11.621ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	10.869m	4.884ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	15.596m	8.064ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	13.589m	7.766ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	2.221h	254.490ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	4.422m	3.798ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	3.740m	6.341ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	4.422m	3.798ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	7.873m	9.902ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	7.873m	9.902ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	5.002m	7.016ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	6.872m	5.758ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	10.215m	6.111ms	1	1	100.00
		chip_sw_aes_idle	2.669m	3.010ms	1	1	100.00
		chip_sw_hmac_enc_idle	3.064m	2.918ms	1	1	100.00
		chip_sw_kmac_idle	1.773m	2.297ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	4.857m	4.483ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	5.539m	5.414ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	5.883m	5.544ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	4.664m	3.756ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	11.007m	9.230ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	6.310m	3.806ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.642m	4.406ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.876m	3.962ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.161m	4.722ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.482m	3.383ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.230m	4.462ms	1	1	100.00
		chip_sw_ast_clk_outputs	8.796m	7.382ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	3.424m	5.514ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.876m	3.962ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.161m	4.722ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	6.180m	4.437ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	10.049m	6.444ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	55.716m	18.294ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.980m	2.878ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	10.263m	5.968ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.907m	3.335ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	18.490m	9.836ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.623m	3.132ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.732m	4.689ms	1	1	100.00
		chip_sw_clkmgr_jitter	1.928m	1.905ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	2.408m	2.955ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	6.181m	4.914ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	11.387m	7.686ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	50.056m	24.632ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	2.065m	2.990ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.263m	2.935ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	12.422m	8.302ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	2.748m	3.320ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	5.974m	4.606ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	22.040m	20.532ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	3.180h	134.617ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	8.796m	7.382ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	6.257m	4.813ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	4.331m	3.386ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	6.766m	6.072ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	10.869m	4.884ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	10.885m	5.379ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	3.744m	4.488ms	1	1	100.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	6.105m	6.898ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	2.252m	3.201ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	27.090m	10.139ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	2.669m	2.999ms	1	1	100.00
		chip_sw_edn_entropy_reqs	13.821m	7.966ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	2.669m	2.999ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	10.885m	5.379ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	2.006m	2.423ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	17.655m	22.925ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	9.565m	5.896ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	10.049m	6.444ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	5.197m	3.286ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	6.180m	4.437ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	1.059h	42.647ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	17.655m	22.925ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	3.757m	3.555ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	13.365m	8.152ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	5.460m	4.291ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	1.059h	42.647ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	5.460m	4.291ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	5.460m	4.291ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	5.460m	4.291ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	5.460m	4.291ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	6.766m	6.072ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	2.243m	4.776ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	8.399m	5.733ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	6.165m	4.556ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	6.165m	4.556ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	2.095m	2.726ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.907m	3.335ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	3.064m	2.918ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	1.987m	2.461ms	0	1	0.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	4.612m	3.683ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	7.621m	5.251ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	5.583m	4.341ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	6.679m	4.661ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	3.944m	3.019ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	13.365m	8.152ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	18.490m	9.836ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	24.558m	10.525ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	25.406m	11.170ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	46.327m	16.976ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	2.086m	2.817ms	1	1	100.00
		chip_sw_kmac_mode_kmac	3.451m	3.043ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.623m	3.132ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	13.365m	8.152ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	6.000m	6.576ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	1.887m	3.357ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	17.883m	8.060ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	1.773m	2.297ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	6.163m	6.049ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	10.478m	8.896ms	1	1	100.00
		chip_tap_straps_rma	3.737m	4.328ms	1	1	100.00
		chip_tap_straps_prod	15.774m	14.034ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.792m	2.944ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	6.000m	6.576ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	6.000m	6.576ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	6.000m	6.576ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	13.555m	6.618ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	5.460m	4.291ms	1	1	100.00
		chip_sw_flash_rma_unlocked	1.059h	42.647ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.545m	3.064ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	11.273m	7.901ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	8.459m	5.760ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	8.000m	6.284ms	1	1	100.00
		chip_sw_lc_ctrl_transition	6.000m	6.576ms	1	1	100.00
		chip_sw_keymgr_key_derivation	13.365m	8.152ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	5.301m	9.703ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	9.423m	7.907ms	1	1	100.00
		chip_prim_tl_access	2.243m	4.776ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	3.424m	5.514ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	6.310m	3.806ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.642m	4.406ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.876m	3.962ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.161m	4.722ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.482m	3.383ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.230m	4.462ms	1	1	100.00
		chip_tap_straps_dev	10.478m	8.896ms	1	1	100.00
		chip_tap_straps_rma	3.737m	4.328ms	1	1	100.00
		chip_tap_straps_prod	15.774m	14.034ms	1	1	100.00
		chip_rv_dm_lc_disabled	4.510m	9.458ms	1	1	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.339m	2.935ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.237m	3.573ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.461m	2.713ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	2.499m	3.384ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	26.778m	33.104ms	1	1	100.00
		chip_rv_dm_lc_disabled	4.510m	9.458ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.143h	49.360ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	1.124h	47.291ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	7.644m	7.108ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	1.141h	48.967ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	26.778m	33.104ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.211m	2.328ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	54.860s	2.232ms	1	1	100.00
		rom_volatile_raw_unlock	58.970s	2.364ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	54.187m	17.334ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	55.716m	18.294ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	10.215m	6.111ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	10.215m	6.111ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	10.215m	6.111ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	4.464m	3.417ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	6.000m	6.576ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	17.655m	22.925ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.464m	3.417ms	1	1	100.00
		chip_sw_keymgr_key_derivation	13.365m	8.152ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	4.937m	4.289ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.267m	3.079ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	17.655m	22.925ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.464m	3.417ms	1	1	100.00
		chip_sw_keymgr_key_derivation	13.365m	8.152ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	4.937m	4.289ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.267m	3.079ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	6.000m	6.576ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	5.083m	5.290ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.792m	2.944ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.545m	3.064ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	11.273m	7.901ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	8.459m	5.760ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	8.000m	6.284ms	1	1	100.00
		chip_sw_lc_ctrl_transition	6.000m	6.576ms	1	1	100.00
		chip_prim_tl_access	2.243m	4.776ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	2.243m	4.776ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	18.850m	9.734ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	4.624m	7.447ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	22.417m	26.199ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	3.741m	7.439ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	6.698m	7.420ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	5.221m	5.159ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	17.820m	24.835ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	12.372m	13.974ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	7.873m	9.902ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	16.190m	13.528ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	5.408m	5.448ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	4.624m	7.447ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	4.229m	3.553ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	32.290m	40.141ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	5.079m	7.334ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	5.694m	5.061ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	23.741m	26.145ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	9.709m	6.421ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	13.550m	10.050ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	27.102m	27.934ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	3.553m	3.069ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	6.766m	6.072ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	5.301m	9.703ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	5.301m	9.703ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	13.550m	10.050ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	23.741m	26.145ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	5.408m	5.448ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	3.740m	6.341ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	3.227m	3.701ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	3.467m	4.557ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	5.098m	5.089ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	12.207m	9.559ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	2.614m	3.089ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	6.766m	6.072ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	15.596m	8.064ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	8.287m	4.954ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	7.888m	4.568ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	3.139m	2.965ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	2.267m	3.079ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	3.467m	4.557ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	3.467m	4.557ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	2.741m	4.076ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	13.036m	13.501ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	3.227m	3.701ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	5.918m	5.296ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	4.849m	6.617ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	3.737m	4.328ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	4.510m	9.458ms	1	1	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	9.787m	5.276ms	1	1	100.00
		chip_plic_all_irqs_10	5.237m	3.248ms	1	1	100.00
		chip_plic_all_irqs_20	5.327m	4.030ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	1.748m	2.106ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	2.465m	2.830ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	41.760m	15.080ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	7.792m	7.099ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	2.771m	2.762ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	3.481m	3.548ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	2.845m	2.639ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	4.937m	4.289ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.732m	4.689ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	5.696m	6.280ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	7.180m	7.790ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	9.423m	7.907ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	6.766m	6.072ms	1	1	100.00
		chip_sw_data_integrity_escalation	6.678m	6.126ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	9.709m	6.421ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	18.137m	23.731ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	2.006m	2.309ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	3.163m	3.593ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	4.909m	4.335ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	18.137m	23.731ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	18.137m	23.731ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	12.563m	11.379ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	12.563m	11.379ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	4.482m	5.242ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	47.413m	34.617ms	0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	2.221m	2.660ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	1.917m	2.226ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	4.849m	4.238ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	5.080m	3.315ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	18.178m	8.470ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.329h	31.252ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	30.791m	11.755ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	2.913m	2.942ms	1	1	100.00
V2		TOTAL			238	275	86.55
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	2.919m	2.858ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	2.303m	2.630ms	0	1	0.00
V2S		TOTAL			1	2	50.00
V3	chip_sw_coremark	chip_sw_coremark	2.653h	72.463ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	6.811m	4.011ms	0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	2.669m	4.006ms	0	1	0.00
		rom_e2e_jtag_debug_dev	20.195m	11.798ms	1	1	100.00
		rom_e2e_jtag_debug_rma	2.595m	3.471ms	0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	3.407m	3.338ms	1	1	100.00
		rom_e2e_jtag_inject_dev	2.733m	3.700ms	1	1	100.00
		rom_e2e_jtag_inject_rma	3.190m	3.637ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	11.867s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	10.128m	5.750ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	4.790m	2.747ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	14.379m	5.968ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	24.722m	10.471ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.489m	2.085ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	9.395m	5.218ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	56.660s	2.660ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	6.433m	5.958ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	4.689m	5.367ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	5.871m	4.942ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	13.550m	10.050ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	2.669m	4.006ms	0	1	0.00
		rom_e2e_jtag_debug_dev	20.195m	11.798ms	1	1	100.00
		rom_e2e_jtag_debug_rma	2.595m	3.471ms	0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	4.952m	5.029ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	6.766m	6.072ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.553h	37.698ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.553h	37.698ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	2.790m	3.425ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	6.073m	4.382ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	48.638m	18.578ms	1	1	100.00
V3		TOTAL			19	23	82.61
	Unmapped tests	chip_sival_flash_info_access	3.284m	3.192ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	6.705m	5.718ms	1	1	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	2.370m	2.832ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	3.240m	2.879ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	3.555m	3.775ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	10.429s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	2.916m	3.085ms	1	1	100.00
		TOTAL			281	325	86.46

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.103234798497364273693537599499498194825756326518562783589816167514548338561925
    Line 476, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.75405248118955420349358155677423853396454218509349216727364959451620716770482
    Line 490, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.28597858387647636556154511034700379602383857287672963180451150431534783163608
    Line 508, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.60455159957981610876598632244885718857726025317535141753374855546295740377787
    Line 503, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.87251074163666713907176956433838755710794848884702346492365772229587734715695
    Line 504, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.29874206974342656800038352690198196887071045113744650875518258763467773852258
    Line 467, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.62456081230087470499731985823600155262539125411087202008607931166785112991835
    Line 467, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.9634383269264003339043343199668468291422865233672200508839233871026584178556
    Line 474, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.51229338361195570812793744464777665648833311126155677356240186286617983251827
    Line 476, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.69867752828478507446336962008169425476712453819982256619628294651256694221324
    Line 480, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.20016539266357243452036373667916333177404509242529651481577377677124713003617
    Line 501, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.6272611251953970167537064542963651607561431419520935012832675706025331851263
    Line 551, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.96929104013905069999617676745028690609563211696555405449037364065414995658738
    Line 520, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.54018301309532269943439874549757761151865194404000117540031066101134388481544
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.153s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.5295797736227059598578156692165173424750394824511918355871097269487962545595
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 0.154s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.89483226542790194178063038537113849549610645986965079705159277159626955513967
    Line 516, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.92873577979945675607447427624663746606508803927809258798604441107121603546302
    Line 495, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.7581558907151934365855416934750780371858305672905902632093346429599849777692
    Line 516, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.112006669466214668901427583289488896421137756028112161247467488733984286911383
    Line 503, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (jtag_rv_debugger.sv:784) [debugger] Index * appears to be out of bounds has 2 failures:
- Test rom_e2e_jtag_debug_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_debug_test_unlocked0.23862178607927568135930047775023412550115239756015377128406104128134739266272
    Line 433, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log
```
  UVM_ERROR @ 4006.293557 us: (jtag_rv_debugger.sv:784) [debugger] Index 3 appears to be out of bounds
  UVM_INFO @ 4006.293557 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_rma has 1 failures.
  - 0.rom_e2e_jtag_debug_rma.44050940377843303510785443464260877495021206239463296486790792015973069312964
    Line 455, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log
```
  UVM_ERROR @ 3471.489996 us: (jtag_rv_debugger.sv:784) [debugger] Index 3 appears to be out of bounds
  UVM_INFO @ 3471.489996 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [*] vs *xz [z]) for MIO[*] has 1 failures:
- Test chip_sw_sleep_pin_mio_dio_val has 1 failures.
  - 0.chip_sw_sleep_pin_mio_dio_val.90386925255827507059122332959640315534802785169107637229502095655639805759384
    Line 593, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_pin_mio_dio_val/latest/run.log
```
  UVM_ERROR @ 3138.560000 us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (0x0 [0] vs 0xz [z]) for MIO[30]
  UVM_INFO @ 3138.560000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.35233194882323338457877066672542158910588111537418040913198441627407665517598
    Line 405, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 2761.557080 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 2761.557080 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@83220) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.78101454214482387543694193931570922418705174256950188175663723870149756868109
Line 420, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 4556.724294 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@83220) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h1  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4556.724294 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:200)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor has 1 failures:
- Test chip_sw_sysrst_ctrl_ec_rst_l has 1 failures.
  - 0.chip_sw_sysrst_ctrl_ec_rst_l.33404403349072646680662644083094482913572273541953981970890507826778542976661
    Line 401, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_ec_rst_l/latest/run.log
```
  UVM_ERROR @ 11378.930756 us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:200)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor
  UVM_INFO @ 11378.930756 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 1 failures.
  - 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.29187776684977316279685348865297912881115138360249960408062887436561468555251
    Line 408, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  UVM_ERROR @ 34617.251006 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 34617.251006 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.51033353965046093607650192342149470252881491488682411428827992826002132410147
    Line 387, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 2749.029429 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 42!
  UVM_INFO @ 2749.029429 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.83335383699938512865023861183704368998595507394070941279539209291205488387890
    Line 388, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3296.457572 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 3296.457572 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:594) virtual_sequencer [Alert %0s fired unexpectedly.] usbdev_fatal_fault has 1 failures:
- Test chip_sw_alert_handler_entropy has 1 failures.
  - 0.chip_sw_alert_handler_entropy.34371732011946265410566481369190310753323992470084599766244910722255061578836
    Line 519, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_entropy/latest/run.log
```
  UVM_ERROR @ 3216.892320 us: (cip_base_vseq.sv:594) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] usbdev_fatal_fault
  UVM_INFO @ 3216.892320 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: *. has 1 failures:
- Test chip_sw_hmac_oneshot has 1 failures.
  - 0.chip_sw_hmac_oneshot.90584457318593148643668820157770078979441728644694855706057313241114380156221
    Line 391, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_oneshot/latest/run.log
```
  UVM_ERROR @ 2460.802712 us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: 8000534a.
  UVM_INFO @ 2460.802712 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32136) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.46248390466089962564414042412858849565432068223919433920024752406597845865138
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 1878.721689 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32136) { a_addr: 'h1074c  a_data: 'h64c50f5e  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h4  a_user: 'h1a945  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 1878.721689 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. has 1 failures:
- Test chip_sw_rv_core_ibex_lockstep_glitch has 1 failures.
  - 0.chip_sw_rv_core_ibex_lockstep_glitch.86036936567670326099785686503837717824961864784045693702580086641290131388519
    Line 404, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
```
  UVM_FATAL @ 2630.496780 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
  UVM_INFO @ 2630.496780 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.77570727397512271537838945960959546519645557262345935757616474311944223811504
    Line 392, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 3130.906500 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3130.906500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.73628523576215649069502303843348381293318671055252049577781371082931291242048
    Line 411, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 3456.208000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3456.208000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:196) [chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= * (* [*] vs * [*]) has 1 failures:
- Test chip_sw_power_virus has 1 failures.
  - 0.chip_sw_power_virus.47049385842965264951760316318661536752906272981374617891568068558053320264189
    Line 461, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 4011.394272 us: (chip_sw_power_virus_vseq.sv:196) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 4011.394272 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.75913172612263375040671178754259468622677289453157291888897882892246999480322
    Line 513, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.74589271865498840324463712918749903499129481664806544736035327523217551123258
    Line 521, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32064) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

0.chip_csr_mem_rw_with_rand_reset.28291977906539127752555573367913233228376066639379637703001925953268979736988
Line 221, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2096.638975 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32064) { a_addr: 'h10568  a_data: 'h4fac7dbc  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h11  a_opcode: 'h4  a_user: 'h1b662  d_param: 'h0  d_source: 'h11  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2096.638975 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---