ADC_CTRL Simulation Results

Wednesday September 03 2025 16:00:25 UTC

GitHub Revision: 83b8114

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	11.770s	5.965ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	1.010s	1.064ms	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.050s	529.628us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.768m	52.279ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	2.380s	1.130ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	1.050s	698.901us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.050s	529.628us	1	1	100.00
		adc_ctrl_csr_aliasing	2.380s	1.130ms	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	8.473m	331.604ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	3.478m	504.998ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	4.581m	161.638ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	4.977m	333.911ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	3.518m	533.009ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	1.288m	201.394ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	10.869m	362.744ms	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	29.910s	159.318ms	1	1	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	4.550s	3.106ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.055m	34.686ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	1.251m	88.131ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	4.237m	133.849ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	1.850s	513.912us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	1.770s	475.271us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	1.560s	391.426us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	1.560s	391.426us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	1.010s	1.064ms	1	1	100.00
		adc_ctrl_csr_rw	1.050s	529.628us	1	1	100.00
		adc_ctrl_csr_aliasing	2.380s	1.130ms	1	1	100.00
		adc_ctrl_same_csr_outstanding	5.780s	2.364ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	1.010s	1.064ms	1	1	100.00
		adc_ctrl_csr_rw	1.050s	529.628us	1	1	100.00
		adc_ctrl_csr_aliasing	2.380s	1.130ms	1	1	100.00
		adc_ctrl_same_csr_outstanding	5.780s	2.364ms	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	tl_intg_err	adc_ctrl_sec_cm	4.180s	7.773ms	1	1	100.00
		adc_ctrl_tl_intg_err	7.400s	3.760ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	7.400s	3.760ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	10.210s	3.585ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			25	25	100.00