ENTROPY_SRC/RNG_4BITS Simulation Results

Wednesday September 03 2025 16:00:25 UTC

GitHub Revision: 83b8114

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	entropy_src_smoke	4.000s	141.294us	1	1	100.00
V1	csr_hw_reset	entropy_src_csr_hw_reset	3.000s	68.392us	1	1	100.00
V1	csr_rw	entropy_src_csr_rw	3.000s	17.565us	1	1	100.00
V1	csr_bit_bash	entropy_src_csr_bit_bash	8.000s	417.721us	1	1	100.00
V1	csr_aliasing	entropy_src_csr_aliasing	6.000s	259.386us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	entropy_src_csr_mem_rw_with_rand_reset	3.000s	33.940us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	entropy_src_csr_rw	3.000s	17.565us	1	1	100.00
		entropy_src_csr_aliasing	6.000s	259.386us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	entropy_src_smoke	4.000s	141.294us	1	1	100.00
		entropy_src_rng	50.000s	12.135ms	1	1	100.00
		entropy_src_fw_ov	32.000s	3.186ms	0	1	0.00
V2	firmware_mode	entropy_src_fw_ov	32.000s	3.186ms	0	1	0.00
V2	rng_mode	entropy_src_rng	50.000s	12.135ms	1	1	100.00
V2	rng_max_rate	entropy_src_rng_max_rate	1.617m	11.218ms	1	1	100.00
V2	health_checks	entropy_src_rng	50.000s	12.135ms	1	1	100.00
V2	conditioning	entropy_src_rng	50.000s	12.135ms	1	1	100.00
V2	interrupts	entropy_src_rng	50.000s	12.135ms	1	1	100.00
		entropy_src_intr	10.000s	397.957us	1	1	100.00
V2	alerts	entropy_src_rng	50.000s	12.135ms	1	1	100.00
		entropy_src_functional_alerts	6.000s	363.572us	1	1	100.00
V2	stress_all	entropy_src_stress_all	14.000s	1.847ms	0	1	0.00
V2	functional_errors	entropy_src_functional_errors	4.000s	49.783us	1	1	100.00
V2	firmware_ov_read_contiguous_data	entropy_src_fw_ov_contiguous	21.000s	1.418ms	1	1	100.00
V2	intr_test	entropy_src_intr_test	4.000s	107.888us	1	1	100.00
V2	alert_test	entropy_src_alert_test	3.000s	194.017us	1	1	100.00
V2	tl_d_oob_addr_access	entropy_src_tl_errors	6.000s	73.630us	1	1	100.00
V2	tl_d_illegal_access	entropy_src_tl_errors	6.000s	73.630us	1	1	100.00
V2	tl_d_outstanding_access	entropy_src_csr_hw_reset	3.000s	68.392us	1	1	100.00
		entropy_src_csr_rw	3.000s	17.565us	1	1	100.00
		entropy_src_csr_aliasing	6.000s	259.386us	1	1	100.00
		entropy_src_same_csr_outstanding	5.000s	888.443us	1	1	100.00
V2	tl_d_partial_access	entropy_src_csr_hw_reset	3.000s	68.392us	1	1	100.00
		entropy_src_csr_rw	3.000s	17.565us	1	1	100.00
		entropy_src_csr_aliasing	6.000s	259.386us	1	1	100.00
		entropy_src_same_csr_outstanding	5.000s	888.443us	1	1	100.00
V2		TOTAL			10	12	83.33
V2S	tl_intg_err	entropy_src_sec_cm	3.000s	57.563us	1	1	100.00
		entropy_src_tl_intg_err	8.000s	199.160us	1	1	100.00
V2S	sec_cm_config_regwen	entropy_src_rng	50.000s	12.135ms	1	1	100.00
		entropy_src_cfg_regwen	4.000s	23.016us	1	1	100.00
V2S	sec_cm_config_mubi	entropy_src_rng	50.000s	12.135ms	1	1	100.00
V2S	sec_cm_config_redun	entropy_src_rng	50.000s	12.135ms	1	1	100.00
V2S	sec_cm_intersig_mubi	entropy_src_rng	50.000s	12.135ms	1	1	100.00
		entropy_src_fw_ov	32.000s	3.186ms	0	1	0.00
V2S	sec_cm_main_sm_fsm_sparse	entropy_src_functional_errors	4.000s	49.783us	1	1	100.00
		entropy_src_sec_cm	3.000s	57.563us	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	entropy_src_functional_errors	4.000s	49.783us	1	1	100.00
		entropy_src_sec_cm	3.000s	57.563us	1	1	100.00
V2S	sec_cm_rng_bkgn_chk	entropy_src_rng	50.000s	12.135ms	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	entropy_src_functional_errors	4.000s	49.783us	1	1	100.00
		entropy_src_sec_cm	3.000s	57.563us	1	1	100.00
V2S	sec_cm_ctr_redun	entropy_src_functional_errors	4.000s	49.783us	1	1	100.00
		entropy_src_sec_cm	3.000s	57.563us	1	1	100.00
V2S	sec_cm_ctr_local_esc	entropy_src_functional_errors	4.000s	49.783us	1	1	100.00
V2S	sec_cm_esfinal_rdata_bus_consistency	entropy_src_functional_alerts	6.000s	363.572us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	entropy_src_tl_intg_err	8.000s	199.160us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	external_health_tests	entropy_src_rng_with_xht_rsps	6.500m	20.067ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			20	22	90.91

Failure Buckets

• UVM_ERROR (cip_base_scoreboard.sv:354) scoreboard [scoreboard] alert recov_alert did not trigger max_delay:* has 1 failures:

  • Test entropy_src_stress_all has 1 failures.

    • 0.entropy_src_stress_all.41038866486557123417840195946746338060073392791793329981071758406705826243584
      Line 656, in log /nightly/current_run/scratch/master/entropy_src-sim-xcelium/0.entropy_src_stress_all/latest/run.log

        UVM_ERROR @ 1846844640 ps: (cip_base_scoreboard.sv:354) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_alert did not trigger max_delay:0
        UVM_INFO @ 1846844640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:268) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_alert triggered unexpectedly has 1 failures:

  • Test entropy_src_fw_ov has 1 failures.

    • 0.entropy_src_fw_ov.60901610428610511231914297760241367700944486854429141805726727150709454888341
      Line 250, in log /nightly/current_run/scratch/master/entropy_src-sim-xcelium/0.entropy_src_fw_ov/latest/run.log

        UVM_ERROR @ 3185520410 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_alert triggered unexpectedly
        UVM_INFO @ 3185520410 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---