HMAC Simulation Results

Wednesday September 03 2025 16:00:25 UTC

GitHub Revision: 83b8114

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 6.960s 918.155us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 0.970s 36.063us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.040s 37.292us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 4.290s 535.401us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 4.420s 389.317us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 1.270s 60.704us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.040s 37.292us 1 1 100.00
hmac_csr_aliasing 4.420s 389.317us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 50.280s 4.089ms 1 1 100.00
V2 back_pressure hmac_back_pressure 21.140s 986.757us 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 7.840s 334.168us 1 1 100.00
hmac_test_sha384_vectors 5.794m 55.196ms 1 1 100.00
hmac_test_sha512_vectors 5.681m 20.562ms 1 1 100.00
hmac_test_hmac256_vectors 5.440s 663.234us 1 1 100.00
hmac_test_hmac384_vectors 10.910s 1.303ms 1 1 100.00
hmac_test_hmac512_vectors 10.650s 330.975us 1 1 100.00
V2 burst_wr hmac_burst_wr 5.410s 499.957us 1 1 100.00
V2 datapath_stress hmac_datapath_stress 5.450m 6.383ms 1 1 100.00
V2 error hmac_error 51.260s 16.505ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 31.680s 3.364ms 1 1 100.00
V2 save_and_restore hmac_smoke 6.960s 918.155us 1 1 100.00
hmac_long_msg 50.280s 4.089ms 1 1 100.00
hmac_back_pressure 21.140s 986.757us 1 1 100.00
hmac_datapath_stress 5.450m 6.383ms 1 1 100.00
hmac_burst_wr 5.410s 499.957us 1 1 100.00
hmac_stress_all 14.490s 1.069ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 6.960s 918.155us 1 1 100.00
hmac_long_msg 50.280s 4.089ms 1 1 100.00
hmac_back_pressure 21.140s 986.757us 1 1 100.00
hmac_datapath_stress 5.450m 6.383ms 1 1 100.00
hmac_wipe_secret 31.680s 3.364ms 1 1 100.00
hmac_test_sha256_vectors 7.840s 334.168us 1 1 100.00
hmac_test_sha384_vectors 5.794m 55.196ms 1 1 100.00
hmac_test_sha512_vectors 5.681m 20.562ms 1 1 100.00
hmac_test_hmac256_vectors 5.440s 663.234us 1 1 100.00
hmac_test_hmac384_vectors 10.910s 1.303ms 1 1 100.00
hmac_test_hmac512_vectors 10.650s 330.975us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 6.960s 918.155us 1 1 100.00
hmac_long_msg 50.280s 4.089ms 1 1 100.00
hmac_back_pressure 21.140s 986.757us 1 1 100.00
hmac_datapath_stress 5.450m 6.383ms 1 1 100.00
hmac_burst_wr 5.410s 499.957us 1 1 100.00
hmac_error 51.260s 16.505ms 1 1 100.00
hmac_wipe_secret 31.680s 3.364ms 1 1 100.00
hmac_test_sha256_vectors 7.840s 334.168us 1 1 100.00
hmac_test_sha384_vectors 5.794m 55.196ms 1 1 100.00
hmac_test_sha512_vectors 5.681m 20.562ms 1 1 100.00
hmac_test_hmac256_vectors 5.440s 663.234us 1 1 100.00
hmac_test_hmac384_vectors 10.910s 1.303ms 1 1 100.00
hmac_test_hmac512_vectors 10.650s 330.975us 1 1 100.00
hmac_stress_all 14.490s 1.069ms 1 1 100.00
V2 stress_all hmac_stress_all 14.490s 1.069ms 1 1 100.00
V2 alert_test hmac_alert_test 0.760s 96.039us 1 1 100.00
V2 intr_test hmac_intr_test 0.790s 37.721us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.060s 99.180us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.060s 99.180us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 0.970s 36.063us 1 1 100.00
hmac_csr_rw 1.040s 37.292us 1 1 100.00
hmac_csr_aliasing 4.420s 389.317us 1 1 100.00
hmac_same_csr_outstanding 1.290s 155.454us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 0.970s 36.063us 1 1 100.00
hmac_csr_rw 1.040s 37.292us 1 1 100.00
hmac_csr_aliasing 4.420s 389.317us 1 1 100.00
hmac_same_csr_outstanding 1.290s 155.454us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 0.920s 179.316us 1 1 100.00
hmac_tl_intg_err 1.690s 656.397us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 1.690s 656.397us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 6.960s 918.155us 1 1 100.00
V3 stress_reset hmac_stress_reset 3.100s 618.040us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 1.851m 1.130ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 2.500s 192.775us 1 1 100.00
TOTAL 28 28 100.00