I2C Simulation Results

Wednesday September 03 2025 16:00:25 UTC

GitHub Revision: 83b8114

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	20.600s	1.406ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	8.830s	3.433ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.680s	52.668us	1	1	100.00
V1	csr_rw	i2c_csr_rw	0.750s	151.762us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	3.280s	119.172us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.500s	95.105us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	0.990s	41.238us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.750s	151.762us	1	1	100.00
		i2c_csr_aliasing	1.500s	95.105us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	1.680s	202.389us	0	1	0.00
V2	host_stress_all	i2c_host_stress_all	2.847m	24.946ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	42.750s	5.208ms	1	1	100.00
V2	host_override	i2c_host_override	0.880s	129.964us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	2.862m	4.147ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	1.606m	4.232ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	0.960s	80.108us	1	1	100.00
		i2c_host_fifo_fmt_empty	13.830s	377.022us	1	1	100.00
		i2c_host_fifo_reset_rx	8.370s	212.573us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	2.647m	7.191ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	5.750s	3.866ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	2.760s	646.276us	0	1	0.00
V2	target_glitch	i2c_target_glitch	1.810s	453.523us	0	1	0.00
V2	target_stress_all	i2c_target_stress_all	14.971m	60.509ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	4.220s	3.308ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	8.440s	5.004ms	1	1	100.00
		i2c_target_intr_smoke	4.170s	1.116ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.090s	724.880us	1	1	100.00
		i2c_target_fifo_reset_tx	0.860s	682.235us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	5.186m	61.059ms	1	1	100.00
		i2c_target_stress_rd	8.440s	5.004ms	1	1	100.00
		i2c_target_intr_stress_wr	3.650s	13.116ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.510s	1.374ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	5.230s	1.313ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	3.610s	2.030ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	1.490s	315.658us	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.610s	1.243ms	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.700s	2.301ms	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	42.750s	5.208ms	1	1	100.00
		i2c_host_perf_precise	1.500s	419.198us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	5.750s	3.866ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	3.320s	360.026us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.160s	2.076ms	1	1	100.00
		i2c_target_nack_acqfull_addr	2.150s	819.787us	1	1	100.00
		i2c_target_nack_txstretch	1.510s	326.749us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	6.570s	942.630us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	1.660s	2.032ms	1	1	100.00
V2	alert_test	i2c_alert_test	0.590s	17.681us	1	1	100.00
V2	intr_test	i2c_intr_test	0.820s	45.274us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	1.630s	737.567us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	1.630s	737.567us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.680s	52.668us	1	1	100.00
		i2c_csr_rw	0.750s	151.762us	1	1	100.00
		i2c_csr_aliasing	1.500s	95.105us	1	1	100.00
		i2c_same_csr_outstanding	0.980s	52.307us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.680s	52.668us	1	1	100.00
		i2c_csr_rw	0.750s	151.762us	1	1	100.00
		i2c_csr_aliasing	1.500s	95.105us	1	1	100.00
		i2c_same_csr_outstanding	0.980s	52.307us	1	1	100.00
V2		TOTAL			34	38	89.47
V2S	tl_intg_err	i2c_tl_intg_err	1.350s	567.636us	1	1	100.00
		i2c_sec_cm	0.830s	133.829us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.350s	567.636us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	9.020s	783.689us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.800s	750.607us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	0.870s	16.249us	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			43	50	86.00

Failure Buckets

• UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 3 failures:

  • Test i2c_host_error_intr has 1 failures.

    • 0.i2c_host_error_intr.86064427722335258443465387088758961738299118668544668903960172761802715269022
      Line 107, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

        UVM_ERROR @ 202389475 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @ 202389475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_host_stress_all has 1 failures.

    • 0.i2c_host_stress_all.3383415425915400278765316381600320342639120388855858629402258724078363253754
      Line 129, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

        UVM_ERROR @ 24945876520 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @ 24945876520 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.104841388603665822486428503925507933274461257560168604632404933465515774012457
      Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  16249372 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @  16249372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_target_glitch has 1 failures.

    • 0.i2c_target_glitch.101854020633832386504020550636851545865227882543963226361055536296070779396794
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

        UVM_ERROR @ 453522629 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
        UVM_INFO @ 453522629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.113271463515106286939519273081852749384494609854466473059870325978151918420731
      Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

            Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
        UVM_ERROR @ 750607163 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
        UVM_INFO @ 750607163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:945) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.282166116092771154170231580079995610492139279435924416251806812293344940936
      Line 87, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 783688574 ps: (cip_base_vseq.sv:945) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 783688574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

  • Test i2c_host_mode_toggle has 1 failures.

    • 0.i2c_host_mode_toggle.22379011484621206257039599598277226394823574449038607773881704430952712212115
      Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

        UVM_ERROR @ 646276152 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
        ----------------------------------------------------
        Name            Type                Size  Value
        ----------------------------------------------------
        mon_dut_item    i2c_item            -     @79629