KEYMGR Simulation Results

Wednesday September 03 2025 16:00:25 UTC

GitHub Revision: 83b8114

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	3.170s	347.439us	1	1	100.00
V1	random	keymgr_random	2.380s	45.870us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.060s	47.267us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	0.850s	72.425us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	11.090s	654.890us	1	1	100.00
V1	csr_aliasing	keymgr_csr_aliasing	4.270s	1.026ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	0.930s	35.203us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	0.850s	72.425us	1	1	100.00
		keymgr_csr_aliasing	4.270s	1.026ms	1	1	100.00
V1		TOTAL			7	7	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	3.880s	72.432us	1	1	100.00
V2	sideload	keymgr_sideload	1.450s	22.096us	1	1	100.00
		keymgr_sideload_kmac	11.580s	663.542us	1	1	100.00
		keymgr_sideload_aes	2.050s	145.559us	1	1	100.00
		keymgr_sideload_otbn	4.260s	193.025us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	3.220s	102.795us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	3.210s	89.470us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	2.100s	32.488us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	2.460s	58.489us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	16.730s	9.246ms	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	2.330s	128.538us	1	1	100.00
V2	stress_all	keymgr_stress_all	9.870s	262.998us	1	1	100.00
V2	intr_test	keymgr_intr_test	0.810s	10.801us	1	1	100.00
V2	alert_test	keymgr_alert_test	0.910s	53.650us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	1.780s	318.519us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	1.780s	318.519us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.060s	47.267us	1	1	100.00
		keymgr_csr_rw	0.850s	72.425us	1	1	100.00
		keymgr_csr_aliasing	4.270s	1.026ms	1	1	100.00
		keymgr_same_csr_outstanding	1.920s	503.935us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.060s	47.267us	1	1	100.00
		keymgr_csr_rw	0.850s	72.425us	1	1	100.00
		keymgr_csr_aliasing	4.270s	1.026ms	1	1	100.00
		keymgr_same_csr_outstanding	1.920s	503.935us	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	sec_cm_additional_check	keymgr_sec_cm	6.820s	1.689ms	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	6.820s	1.689ms	1	1	100.00
		keymgr_tl_intg_err	3.620s	461.754us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	2.250s	1.082ms	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	2.250s	1.082ms	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	2.250s	1.082ms	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	2.250s	1.082ms	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	5.180s	186.368us	1	1	100.00
V2S	prim_count_check	keymgr_sec_cm	6.820s	1.689ms	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	6.820s	1.689ms	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	3.620s	461.754us	1	1	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	2.250s	1.082ms	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	3.880s	72.432us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	2.380s	45.870us	1	1	100.00
		keymgr_csr_rw	0.850s	72.425us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	2.380s	45.870us	1	1	100.00
		keymgr_csr_rw	0.850s	72.425us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	2.380s	45.870us	1	1	100.00
		keymgr_csr_rw	0.850s	72.425us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	3.210s	89.470us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	16.730s	9.246ms	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	16.730s	9.246ms	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	2.380s	45.870us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	1.820s	59.188us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	6.820s	1.689ms	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	6.820s	1.689ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	6.820s	1.689ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	2.380s	115.499us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	3.210s	89.470us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	6.820s	1.689ms	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	6.820s	1.689ms	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	6.820s	1.689ms	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	2.380s	115.499us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	2.380s	115.499us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	6.820s	1.689ms	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	2.380s	115.499us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	6.820s	1.689ms	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	2.380s	115.499us	1	1	100.00
V2S		TOTAL			6	6	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	6.860s	530.494us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	30	100.00