KMAC/UNMASKED Simulation Results

Wednesday September 03 2025 16:00:25 UTC

GitHub Revision: 83b8114

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	32.670s	1.281ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	0.870s	151.011us	1	1	100.00
V1	csr_rw	kmac_csr_rw	0.990s	20.790us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	13.630s	2.878ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	7.340s	1.718ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.040s	319.393us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	0.990s	20.790us	1	1	100.00
		kmac_csr_aliasing	7.340s	1.718ms	1	1	100.00
V1	mem_walk	kmac_mem_walk	0.860s	12.415us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.250s	42.585us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	11.132m	125.530ms	1	1	100.00
V2	burst_write	kmac_burst_write	7.265m	19.492ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	28.380s	1.804ms	1	1	100.00
		kmac_test_vectors_sha3_256	28.910s	6.877ms	1	1	100.00
		kmac_test_vectors_sha3_384	21.809m	290.502ms	1	1	100.00
		kmac_test_vectors_sha3_512	10.321m	115.185ms	1	1	100.00
		kmac_test_vectors_shake_128	2.358m	40.863ms	1	1	100.00
		kmac_test_vectors_shake_256	4.450m	89.343ms	1	1	100.00
		kmac_test_vectors_kmac	1.550s	118.855us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.080s	64.246us	1	1	100.00
V2	sideload	kmac_sideload	3.273m	7.292ms	1	1	100.00
V2	app	kmac_app	3.191m	13.585ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.630s	218.573us	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	8.050s	1.468ms	1	1	100.00
V2	error	kmac_error	2.818m	15.078ms	1	1	100.00
V2	key_error	kmac_key_error	8.790s	6.358ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	46.900s	10.087ms	0	1	0.00
V2	edn_timeout_error	kmac_edn_timeout_error	18.390s	509.671us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	4.180s	284.476us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	11.230s	1.798ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	1.470s	47.893us	1	1	100.00
V2	stress_all	kmac_stress_all	14.772m	146.721ms	1	1	100.00
V2	intr_test	kmac_intr_test	0.690s	43.658us	1	1	100.00
V2	alert_test	kmac_alert_test	0.670s	48.197us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	1.150s	65.438us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	1.150s	65.438us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	0.870s	151.011us	1	1	100.00
		kmac_csr_rw	0.990s	20.790us	1	1	100.00
		kmac_csr_aliasing	7.340s	1.718ms	1	1	100.00
		kmac_same_csr_outstanding	2.120s	869.426us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	0.870s	151.011us	1	1	100.00
		kmac_csr_rw	0.990s	20.790us	1	1	100.00
		kmac_csr_aliasing	7.340s	1.718ms	1	1	100.00
		kmac_same_csr_outstanding	2.120s	869.426us	1	1	100.00
V2		TOTAL			25	26	96.15
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.310s	45.718us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.310s	45.718us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.310s	45.718us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.310s	45.718us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.240s	97.588us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	25.020s	2.488ms	1	1	100.00
		kmac_tl_intg_err	3.880s	2.331ms	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	3.880s	2.331ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.470s	47.893us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	32.670s	1.281ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	3.273m	7.292ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.310s	45.718us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	25.020s	2.488ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	25.020s	2.488ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	25.020s	2.488ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	32.670s	1.281ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.470s	47.893us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	25.020s	2.488ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	1.031m	6.597ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	32.670s	1.281ms	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.171m	9.512ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			39	40	97.50

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6) has 1 failures:
  • Test kmac_sideload_invalid has 1 failures.

    • 0.kmac_sideload_invalid.9469128829762474446580018646953257094032422106010512828965746537180927639233
      Line 80, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10086956065 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x43561000, Comparison=CompareOpEq, exp_data=0x1, call_count=6)
        UVM_INFO @ 10086956065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---