OTBN Simulation Results

Wednesday September 03 2025 16:00:25 UTC

GitHub Revision: 83b8114

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	14.000s	67.191us	1	1	100.00
V1	single_binary	otbn_single	6.000s	13.035us	1	1	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	5.000s	15.218us	1	1	100.00
V1	csr_rw	otbn_csr_rw	5.000s	20.232us	1	1	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	6.000s	98.740us	1	1	100.00
V1	csr_aliasing	otbn_csr_aliasing	5.000s	24.242us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	7.000s	118.887us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	5.000s	20.232us	1	1	100.00
		otbn_csr_aliasing	5.000s	24.242us	1	1	100.00
V1	mem_walk	otbn_mem_walk	21.000s	673.010us	1	1	100.00
V1	mem_partial_access	otbn_mem_partial_access	10.000s	134.752us	1	1	100.00
V1		TOTAL			9	9	100.00
V2	reset_recovery	otbn_reset	19.000s	107.141us	1	1	100.00
V2	multi_error	otbn_multi_err	39.000s	1.306ms	1	1	100.00
V2	back_to_back	otbn_multi	12.417m	3.061ms	1	1	100.00
V2	stress_all	otbn_stress_all	2.200m	2.437ms	1	1	100.00
V2	lc_escalation	otbn_escalate	14.000s	212.909us	1	1	100.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	7.000s	29.783us	1	1	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	5.000s	45.089us	1	1	100.00
V2	alert_test	otbn_alert_test	5.000s	22.910us	1	1	100.00
V2	intr_test	otbn_intr_test	4.000s	47.895us	1	1	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	8.000s	288.385us	1	1	100.00
V2	tl_d_illegal_access	otbn_tl_errors	8.000s	288.385us	1	1	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	5.000s	15.218us	1	1	100.00
		otbn_csr_rw	5.000s	20.232us	1	1	100.00
		otbn_csr_aliasing	5.000s	24.242us	1	1	100.00
		otbn_same_csr_outstanding	6.000s	30.917us	1	1	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	5.000s	15.218us	1	1	100.00
		otbn_csr_rw	5.000s	20.232us	1	1	100.00
		otbn_csr_aliasing	5.000s	24.242us	1	1	100.00
		otbn_same_csr_outstanding	6.000s	30.917us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	mem_integrity	otbn_imem_err	9.000s	19.565us	1	1	100.00
		otbn_dmem_err	7.000s	14.856us	1	1	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	7.000s	52.394us	1	1	100.00
		otbn_controller_ispr_rdata_err	9.000s	205.643us	1	1	100.00
		otbn_mac_bignum_acc_err	8.000s	226.476us	1	1	100.00
		otbn_urnd_err	7.000s	18.590us	1	1	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	6.000s	10.131us	1	1	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	7.000s	63.596us	1	1	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	5.000s	15.089us	1	1	100.00
V2S	tl_intg_err	otbn_sec_cm	4.000s	2.906us	0	1	0.00
		otbn_tl_intg_err	12.000s	77.749us	1	1	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	19.000s	851.490us	1	1	100.00
V2S	prim_fsm_check	otbn_sec_cm	4.000s	2.906us	0	1	0.00
V2S	prim_count_check	otbn_sec_cm	4.000s	2.906us	0	1	0.00
V2S	sec_cm_mem_scramble	otbn_smoke	14.000s	67.191us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	7.000s	14.856us	1	1	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	9.000s	19.565us	1	1	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	12.000s	77.749us	1	1	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	14.000s	212.909us	1	1	100.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	9.000s	19.565us	1	1	100.00
		otbn_dmem_err	7.000s	14.856us	1	1	100.00
		otbn_zero_state_err_urnd	7.000s	29.783us	1	1	100.00
		otbn_illegal_mem_acc	6.000s	10.131us	1	1	100.00
		otbn_sec_cm	4.000s	2.906us	0	1	0.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	4.000s	2.906us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	otbn_single	6.000s	13.035us	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	9.000s	19.565us	1	1	100.00
		otbn_dmem_err	7.000s	14.856us	1	1	100.00
		otbn_zero_state_err_urnd	7.000s	29.783us	1	1	100.00
		otbn_illegal_mem_acc	6.000s	10.131us	1	1	100.00
		otbn_sec_cm	4.000s	2.906us	0	1	0.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	4.000s	2.906us	0	1	0.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	14.000s	212.909us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	9.000s	19.565us	1	1	100.00
		otbn_dmem_err	7.000s	14.856us	1	1	100.00
		otbn_zero_state_err_urnd	7.000s	29.783us	1	1	100.00
		otbn_illegal_mem_acc	6.000s	10.131us	1	1	100.00
		otbn_sec_cm	4.000s	2.906us	0	1	0.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	4.000s	2.906us	0	1	0.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	6.000s	13.035us	1	1	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	14.000s	147.370us	1	1	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	7.000s	61.679us	1	1	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	25.000s	93.378us	1	1	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	25.000s	93.378us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	9.000s	22.214us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	4.000s	2.906us	0	1	0.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	4.000s	2.906us	0	1	0.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	8.000s	35.905us	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	4.000s	2.906us	0	1	0.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	4.000s	2.906us	0	1	0.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	10.000s	76.461us	1	1	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	10.000s	76.461us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	6.000s	17.754us	1	1	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	6.000s	13.035us	1	1	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	6.000s	13.035us	1	1	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	6.000s	13.035us	1	1	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	12.417m	3.061ms	1	1	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	6.000s	13.035us	1	1	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	6.000s	13.035us	1	1	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	9.000s	91.614us	1	1	100.00
V2S	sec_cm_key_sideload	otbn_single	6.000s	13.035us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	4.000s	2.906us	0	1	0.00
V2S		TOTAL			19	20	95.00
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	4.433m	3.273ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			40	41	97.56

Failure Buckets

• xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1386): Assertion ErrBitsKnown_A has failed has 1 failures:
  • Test otbn_sec_cm has 1 failures.

    • 0.otbn_sec_cm.659612536741507395917054998239101648602782598188112278726761497196118340123
      Line 83, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log

        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1386): (time 2905745 PS) Assertion tb.dut.ErrBitsKnown_A has failed
        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 2905745 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 2905745 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 2905745 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 2905745 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed