PATTGEN Simulation Results

Wednesday September 03 2025 16:00:25 UTC

GitHub Revision: 83b8114

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	8.000s	63.458us	1	1	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	3.000s	21.898us	1	1	100.00
V1	csr_rw	pattgen_csr_rw	2.000s	127.194us	1	1	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	3.000s	235.097us	1	1	100.00
V1	csr_aliasing	pattgen_csr_aliasing	2.000s	72.536us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	3.000s	167.852us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	2.000s	127.194us	1	1	100.00
		pattgen_csr_aliasing	2.000s	72.536us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	perf	pattgen_perf	15.350m	600.000ms	0	1	0.00
V2	cnt_rollover	cnt_rollover	6.000s	46.148us	1	1	100.00
V2	error	pattgen_error	7.000s	51.957us	1	1	100.00
V2	stress_all	pattgen_stress_all	3.000s	84.859us	1	1	100.00
V2	alert_test	pattgen_alert_test	2.000s	58.248us	1	1	100.00
V2	intr_test	pattgen_intr_test	3.000s	14.184us	1	1	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	3.000s	276.857us	1	1	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	3.000s	276.857us	1	1	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	3.000s	21.898us	1	1	100.00
		pattgen_csr_rw	2.000s	127.194us	1	1	100.00
		pattgen_csr_aliasing	2.000s	72.536us	1	1	100.00
		pattgen_same_csr_outstanding	2.000s	50.143us	1	1	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	3.000s	21.898us	1	1	100.00
		pattgen_csr_rw	2.000s	127.194us	1	1	100.00
		pattgen_csr_aliasing	2.000s	72.536us	1	1	100.00
		pattgen_same_csr_outstanding	2.000s	50.143us	1	1	100.00
V2		TOTAL			7	8	87.50
V2S	tl_intg_err	pattgen_tl_intg_err	3.000s	87.763us	1	1	100.00
		pattgen_sec_cm	5.000s	39.386us	1	1	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	3.000s	87.763us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	17.000s	1.624ms	0	1	0.00
V3		TOTAL			0	1	0.00
	Unmapped tests	pattgen_inactive_level	6.000s	94.985us	1	1	100.00
		TOTAL			16	18	88.89

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test pattgen_perf has 1 failures.

    • 0.pattgen_perf.23755790590995312479119374164781407647843602542031575758885237291252431917159
      Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_perf/latest/run.log

        UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:946) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test pattgen_stress_all_with_rand_reset has 1 failures.

    • 0.pattgen_stress_all_with_rand_reset.83073069539966284085917839610663765923017716612583837408430409364479557364340
      Line 277, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1613293115 ps: (cip_base_vseq.sv:946) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_ERROR @ 1613295026 ps: (cip_base_vseq.sv:850) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 1613295026 ps: (cip_base_vseq.sv:853) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
        Issuing reset for run 5/5
        UVM_INFO @ 1613337578 ps: (cip_base_vseq.sv:874) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]