ROM_CTRL/64KB Simulation Results

Wednesday September 03 2025 16:00:25 UTC

GitHub Revision: 83b8114

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 7.680s 1.048ms 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 8.610s 548.945us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 7.860s 310.612us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 7.730s 700.116us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 6.410s 213.448us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 6.080s 743.436us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 7.860s 310.612us 1 1 100.00
rom_ctrl_csr_aliasing 6.410s 213.448us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 6.550s 1.066ms 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 6.520s 1.024ms 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 6.810s 493.901us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 39.510s 17.989ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 11.830s 1.114ms 1 1 100.00
V2 alert_test rom_ctrl_alert_test 6.680s 363.489us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 9.440s 293.478us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 9.440s 293.478us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 8.610s 548.945us 1 1 100.00
rom_ctrl_csr_rw 7.860s 310.612us 1 1 100.00
rom_ctrl_csr_aliasing 6.410s 213.448us 1 1 100.00
rom_ctrl_same_csr_outstanding 8.880s 1.061ms 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 8.610s 548.945us 1 1 100.00
rom_ctrl_csr_rw 7.860s 310.612us 1 1 100.00
rom_ctrl_csr_aliasing 6.410s 213.448us 1 1 100.00
rom_ctrl_same_csr_outstanding 8.880s 1.061ms 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 1.975m 3.831ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 26.770s 1.055ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 3.425m 1.311ms 1 1 100.00
rom_ctrl_tl_intg_err 1.460m 712.778us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 3.425m 1.311ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 3.425m 1.311ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.975m 3.831ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.975m 3.831ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.975m 3.831ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.975m 3.831ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.975m 3.831ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 3.425m 1.311ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 3.425m 1.311ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 7.680s 1.048ms 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 7.680s 1.048ms 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 7.680s 1.048ms 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 1.460m 712.778us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.975m 3.831ms 1 1 100.00
rom_ctrl_kmac_err_chk 11.830s 1.114ms 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 1.975m 3.831ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 1.975m 3.831ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 1.975m 3.831ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 26.770s 1.055ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 3.425m 1.311ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 1.769m 2.180ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00