SPI_DEVICE/1R1W Simulation Results

Wednesday September 03 2025 16:00:25 UTC

GitHub Revision: 83b8114

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	44.880s	4.354ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.110s	37.128us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.260s	135.618us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	9.810s	3.763ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	5.860s	628.729us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.900s	421.247us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.260s	135.618us	1	1	100.00
		spi_device_csr_aliasing	5.860s	628.729us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.750s	19.199us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.650s	26.828us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	0.910s	15.730us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	0.840s	11.824us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	0.680s	4.024us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	3.470s	348.329us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	3.470s	348.329us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	2.160s	737.355us	1	1	100.00
		spi_device_tpm_sts_read	0.730s	22.503us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	12.940s	2.136ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	12.620s	4.135ms	1	1	100.00
		spi_device_flash_all	14.000s	1.047ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	5.000s	466.999us	1	1	100.00
		spi_device_flash_all	14.000s	1.047ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	5.000s	466.999us	1	1	100.00
		spi_device_flash_all	14.000s	1.047ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	14.000s	1.047ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	7.820s	1.780ms	1	1	100.00
		spi_device_flash_all	14.000s	1.047ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	7.820s	1.780ms	1	1	100.00
		spi_device_flash_all	14.000s	1.047ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	7.820s	1.780ms	1	1	100.00
		spi_device_flash_all	14.000s	1.047ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	7.820s	1.780ms	1	1	100.00
		spi_device_flash_all	14.000s	1.047ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	7.820s	1.780ms	1	1	100.00
		spi_device_flash_all	14.000s	1.047ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	12.670s	4.949ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	6.800s	498.611us	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	6.800s	498.611us	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	6.800s	498.611us	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	2.230s	112.447us	1	1	100.00
		spi_device_read_buffer_direct	2.820s	642.512us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	6.800s	498.611us	1	1	100.00
		spi_device_flash_all	14.000s	1.047ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	14.000s	1.047ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	14.000s	1.047ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	4.860s	1.855ms	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	4.860s	1.855ms	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	44.880s	4.354ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	54.370s	27.744ms	1	1	100.00
V2	stress_all	spi_device_stress_all	57.370s	9.683ms	1	1	100.00
V2	alert_test	spi_device_alert_test	0.800s	33.833us	1	1	100.00
V2	intr_test	spi_device_intr_test	0.790s	17.242us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	1.830s	143.277us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	1.830s	143.277us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.110s	37.128us	1	1	100.00
		spi_device_csr_rw	1.260s	135.618us	1	1	100.00
		spi_device_csr_aliasing	5.860s	628.729us	1	1	100.00
		spi_device_same_csr_outstanding	2.170s	86.253us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.110s	37.128us	1	1	100.00
		spi_device_csr_rw	1.260s	135.618us	1	1	100.00
		spi_device_csr_aliasing	5.860s	628.729us	1	1	100.00
		spi_device_same_csr_outstanding	2.170s	86.253us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.140s	150.263us	1	1	100.00
		spi_device_tl_intg_err	11.210s	13.243ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	11.210s	13.243ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	31.760s	2.816ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.70340354439730942120571069697326255799610131673821740817641779020497100840380
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   6669989 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[31])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   6669989 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   6669989 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[927])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.9524097628081479119997143053031675760017523108065037201988012012657939178181
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   1565275 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xb3fc33 [101100111111110000110011] vs 0x0 [0])
        UVM_ERROR @   1584275 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xfe94db [111111101001010011011011] vs 0x0 [0])
        UVM_ERROR @   1613275 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xf163 [1111000101100011] vs 0x0 [0])
        UVM_ERROR @   1705275 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x468047 [10001101000000001000111] vs 0x0 [0])
        UVM_ERROR @   1755275 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xff0a42 [111111110000101001000010] vs 0x0 [0])