SPI_DEVICE/2P Simulation Results

Wednesday September 03 2025 16:00:25 UTC

GitHub Revision: 83b8114

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	24.380s	12.377ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.190s	68.896us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.840s	349.022us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	8.320s	393.699us	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	17.810s	2.411ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.260s	341.937us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.840s	349.022us	1	1	100.00
		spi_device_csr_aliasing	17.810s	2.411ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.700s	13.238us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.220s	140.476us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	0.840s	18.138us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.000s	117.005us	1	1	100.00
V2	mem_cfg	spi_device_ram_cfg	0.720s	41.643us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	3.860s	137.178us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	3.860s	137.178us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	5.110s	4.654ms	1	1	100.00
		spi_device_tpm_sts_read	0.760s	29.688us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	3.280s	797.722us	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	1.870s	162.223us	1	1	100.00
		spi_device_flash_all	1.703m	74.911ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	2.860s	564.945us	1	1	100.00
		spi_device_flash_all	1.703m	74.911ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	2.860s	564.945us	1	1	100.00
		spi_device_flash_all	1.703m	74.911ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	1.703m	74.911ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	6.680s	1.340ms	1	1	100.00
		spi_device_flash_all	1.703m	74.911ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	6.680s	1.340ms	1	1	100.00
		spi_device_flash_all	1.703m	74.911ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	6.680s	1.340ms	1	1	100.00
		spi_device_flash_all	1.703m	74.911ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	6.680s	1.340ms	1	1	100.00
		spi_device_flash_all	1.703m	74.911ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	6.680s	1.340ms	1	1	100.00
		spi_device_flash_all	1.703m	74.911ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	4.510s	1.634ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	11.120s	839.888us	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	11.120s	839.888us	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	11.120s	839.888us	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	6.470s	492.433us	1	1	100.00
		spi_device_read_buffer_direct	2.920s	411.022us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	11.120s	839.888us	1	1	100.00
		spi_device_flash_all	1.703m	74.911ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	1.703m	74.911ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	1.703m	74.911ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	1.640s	282.800us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	1.640s	282.800us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	24.380s	12.377ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	41.470s	60.936ms	1	1	100.00
V2	stress_all	spi_device_stress_all	4.423m	131.980ms	1	1	100.00
V2	alert_test	spi_device_alert_test	0.720s	44.058us	1	1	100.00
V2	intr_test	spi_device_intr_test	0.730s	76.267us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	3.240s	656.218us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	3.240s	656.218us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.190s	68.896us	1	1	100.00
		spi_device_csr_rw	1.840s	349.022us	1	1	100.00
		spi_device_csr_aliasing	17.810s	2.411ms	1	1	100.00
		spi_device_same_csr_outstanding	2.430s	571.435us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.190s	68.896us	1	1	100.00
		spi_device_csr_rw	1.840s	349.022us	1	1	100.00
		spi_device_csr_aliasing	17.810s	2.411ms	1	1	100.00
		spi_device_same_csr_outstanding	2.430s	571.435us	1	1	100.00
V2		TOTAL			22	22	100.00
V2S	tl_intg_err	spi_device_sec_cm	0.990s	359.320us	1	1	100.00
		spi_device_tl_intg_err	10.730s	2.758ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	10.730s	2.758ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	1.289m	10.025ms	1	1	100.00
		TOTAL			33	33	100.00