SPI_HOST Simulation Results

Wednesday September 03 2025 16:00:25 UTC

GitHub Revision: 83b8114

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	21.000s	4.631ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	3.000s	18.217us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	3.000s	15.940us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	3.000s	202.577us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	2.000s	75.018us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	3.000s	37.189us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	3.000s	15.940us	1	1	100.00
		spi_host_csr_aliasing	2.000s	75.018us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	2.000s	16.197us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	2.000s	48.235us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	3.000s	103.859us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	4.000s	128.125us	1	1	100.00
		spi_host_error_cmd	3.000s	21.758us	1	1	100.00
		spi_host_event	6.000s	393.155us	1	1	100.00
V2	clock_rate	spi_host_speed	3.000s	74.736us	1	1	100.00
V2	speed	spi_host_speed	3.000s	74.736us	1	1	100.00
V2	chip_select_timing	spi_host_speed	3.000s	74.736us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	5.000s	195.978us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	2.000s	151.505us	1	1	100.00
V2	cpol_cpha	spi_host_speed	3.000s	74.736us	1	1	100.00
V2	full_cycle	spi_host_speed	3.000s	74.736us	1	1	100.00
V2	duplex	spi_host_smoke	21.000s	4.631ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	21.000s	4.631ms	1	1	100.00
V2	stress_all	spi_host_stress_all	16.000s	719.820us	1	1	100.00
V2	spien	spi_host_spien	8.000s	1.241ms	1	1	100.00
V2	stall	spi_host_status_stall	9.000s	532.998us	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	6.000s	463.449us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	4.000s	128.125us	1	1	100.00
V2	alert_test	spi_host_alert_test	2.000s	30.729us	1	1	100.00
V2	intr_test	spi_host_intr_test	2.000s	78.015us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	3.000s	54.715us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	3.000s	54.715us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	3.000s	18.217us	1	1	100.00
		spi_host_csr_rw	3.000s	15.940us	1	1	100.00
		spi_host_csr_aliasing	2.000s	75.018us	1	1	100.00
		spi_host_same_csr_outstanding	2.000s	163.115us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	3.000s	18.217us	1	1	100.00
		spi_host_csr_rw	3.000s	15.940us	1	1	100.00
		spi_host_csr_aliasing	2.000s	75.018us	1	1	100.00
		spi_host_same_csr_outstanding	2.000s	163.115us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	3.000s	100.285us	1	1	100.00
		spi_host_sec_cm	2.000s	67.579us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	3.000s	100.285us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	50.000s	1.203ms	1	1	100.00
		TOTAL			26	26	100.00