SRAM_CTRL/MAIN Simulation Results

Wednesday September 03 2025 16:00:25 UTC

GitHub Revision: 83b8114

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	10.350s	896.579us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.800s	59.655us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.950s	14.733us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.200s	86.506us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.800s	16.105us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.700s	1.936ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.950s	14.733us	1	1	100.00
		sram_ctrl_csr_aliasing	0.800s	16.105us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	1.825m	2.743ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.811m	19.645ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	12.989m	44.664ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.703m	5.298ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	26.720m	194.504ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	1.126m	1.785ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	16.850s	7.788ms	1	1	100.00
V2	executable	sram_ctrl_executable	8.911m	30.428ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	18.530s	3.257ms	1	1	100.00
		sram_ctrl_partial_access_b2b	4.737m	7.398ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	15.210s	3.018ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	35.060s	810.729us	1	1	100.00
		sram_ctrl_throughput_w_readback	8.870s	3.184ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	7.611m	44.524ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	2.670s	349.663us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	29.068m	147.317ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.920s	13.915us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.150s	25.952us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.150s	25.952us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.800s	59.655us	1	1	100.00
		sram_ctrl_csr_rw	0.950s	14.733us	1	1	100.00
		sram_ctrl_csr_aliasing	0.800s	16.105us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.730s	85.233us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.800s	59.655us	1	1	100.00
		sram_ctrl_csr_rw	0.950s	14.733us	1	1	100.00
		sram_ctrl_csr_aliasing	0.800s	16.105us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.730s	85.233us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	18.370s	7.903ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.660s	28.813us	0	1	0.00
		sram_ctrl_tl_intg_err	1.450s	82.006us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.660s	28.813us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.450s	82.006us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	7.611m	44.524ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	7.611m	44.524ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.950s	14.733us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	8.911m	30.428ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	8.911m	30.428ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	8.911m	30.428ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	16.850s	7.788ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	3.820s	703.830us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	18.370s	7.903ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	7.070s	2.739ms	0	1	0.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	10.350s	896.579us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	10.350s	896.579us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	8.911m	30.428ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.660s	28.813us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	16.850s	7.788ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.660s	28.813us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.660s	28.813us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	10.350s	896.579us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.660s	28.813us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	6.200s	259.460us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 1 failures:

  • Test sram_ctrl_readback_err has 1 failures.

    • 0.sram_ctrl_readback_err.51859531343141955420640549912977569163292596871689740867819582644348321177801
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 2739028440 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x4c) != exp (0x58)
        UVM_INFO @ 2739028440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.75174378180324527259557974391818756546620609364650700548870570414553223882338
      Line 99, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  28813109 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  28813109 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---