SYSRST_CTRL Simulation Results

Wednesday September 03 2025 16:00:25 UTC

GitHub Revision: 83b8114

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sysrst_ctrl_smoke 1.580s 2.124ms 1 1 100.00
V1 input_output_inverted sysrst_ctrl_in_out_inverted 4.010s 2.467ms 1 1 100.00
V1 combo_detect_ec_rst sysrst_ctrl_combo_detect_ec_rst 2.810s 2.213ms 1 1 100.00
V1 combo_detect_ec_rst_with_pre_cond sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 5.350s 2.511ms 1 1 100.00
V1 csr_hw_reset sysrst_ctrl_csr_hw_reset 5.820s 4.039ms 1 1 100.00
V1 csr_rw sysrst_ctrl_csr_rw 2.980s 2.062ms 1 1 100.00
V1 csr_bit_bash sysrst_ctrl_csr_bit_bash 46.260s 39.268ms 1 1 100.00
V1 csr_aliasing sysrst_ctrl_csr_aliasing 3.240s 3.201ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset sysrst_ctrl_csr_mem_rw_with_rand_reset 1.790s 2.132ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr sysrst_ctrl_csr_rw 2.980s 2.062ms 1 1 100.00
sysrst_ctrl_csr_aliasing 3.240s 3.201ms 1 1 100.00
V1 TOTAL 9 9 100.00
V2 combo_detect sysrst_ctrl_combo_detect 1.396m 168.697ms 1 1 100.00
V2 combo_detect_with_pre_cond sysrst_ctrl_combo_detect_with_pre_cond 1.005m 86.842ms 1 1 100.00
V2 auto_block_key_outputs sysrst_ctrl_auto_blk_key_output 2.280s 3.543ms 1 1 100.00
V2 keyboard_input_triggered_interrupt sysrst_ctrl_edge_detect 1.710s 2.384ms 1 1 100.00
V2 pin_output_keyboard_inversion_control sysrst_ctrl_pin_override_test 2.220s 2.530ms 1 1 100.00
V2 pin_input_value_accessibility sysrst_ctrl_pin_access_test 4.680s 2.089ms 1 1 100.00
V2 ec_power_on_reset sysrst_ctrl_ec_pwr_on_rst 1.170s 2.656ms 1 1 100.00
V2 flash_write_protect_output sysrst_ctrl_flash_wr_prot_out 1.910s 2.631ms 1 1 100.00
V2 ultra_low_power_test sysrst_ctrl_ultra_low_pwr 2.460s 9.416ms 1 1 100.00
V2 sysrst_ctrl_feature_disable sysrst_ctrl_feature_disable 1.130m 37.793ms 1 1 100.00
V2 stress_all sysrst_ctrl_stress_all 30.160s 13.754ms 1 1 100.00
V2 alert_test sysrst_ctrl_alert_test 2.560s 2.030ms 1 1 100.00
V2 intr_test sysrst_ctrl_intr_test 2.640s 2.014ms 1 1 100.00
V2 tl_d_oob_addr_access sysrst_ctrl_tl_errors 4.450s 2.077ms 1 1 100.00
V2 tl_d_illegal_access sysrst_ctrl_tl_errors 4.450s 2.077ms 1 1 100.00
V2 tl_d_outstanding_access sysrst_ctrl_csr_hw_reset 5.820s 4.039ms 1 1 100.00
sysrst_ctrl_csr_rw 2.980s 2.062ms 1 1 100.00
sysrst_ctrl_csr_aliasing 3.240s 3.201ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 9.580s 10.302ms 1 1 100.00
V2 tl_d_partial_access sysrst_ctrl_csr_hw_reset 5.820s 4.039ms 1 1 100.00
sysrst_ctrl_csr_rw 2.980s 2.062ms 1 1 100.00
sysrst_ctrl_csr_aliasing 3.240s 3.201ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 9.580s 10.302ms 1 1 100.00
V2 TOTAL 15 15 100.00
V2S tl_intg_err sysrst_ctrl_sec_cm 22.610s 22.024ms 1 1 100.00
sysrst_ctrl_tl_intg_err 1.403m 42.488ms 1 1 100.00
V2S sec_cm_bus_integrity sysrst_ctrl_tl_intg_err 1.403m 42.488ms 1 1 100.00
V2S TOTAL 2 2 100.00
V3 stress_all_with_rand_reset sysrst_ctrl_stress_all_with_rand_reset 5.150s 6.651ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 27 27 100.00