UART Simulation Results

Wednesday September 03 2025 16:00:25 UTC

GitHub Revision: 83b8114

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	22.090s	6.270ms	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.780s	13.360us	1	1	100.00
V1	csr_rw	uart_csr_rw	0.650s	93.803us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.190s	193.683us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	0.620s	26.804us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	0.700s	17.971us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.650s	93.803us	1	1	100.00
		uart_csr_aliasing	0.620s	26.804us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	42.980s	31.705ms	1	1	100.00
V2	parity	uart_smoke	22.090s	6.270ms	1	1	100.00
		uart_tx_rx	42.980s	31.705ms	1	1	100.00
V2	parity_error	uart_intr	23.330s	16.074ms	1	1	100.00
		uart_rx_parity_err	35.110s	176.586ms	1	1	100.00
V2	watermark	uart_tx_rx	42.980s	31.705ms	1	1	100.00
		uart_intr	23.330s	16.074ms	1	1	100.00
V2	fifo_full	uart_fifo_full	24.030s	16.077ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	11.460s	19.332ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	25.920s	72.232ms	1	1	100.00
V2	rx_frame_err	uart_intr	23.330s	16.074ms	1	1	100.00
V2	rx_break_err	uart_intr	23.330s	16.074ms	1	1	100.00
V2	rx_timeout	uart_intr	23.330s	16.074ms	1	1	100.00
V2	perf	uart_perf	3.743m	11.534ms	1	1	100.00
V2	sys_loopback	uart_loopback	0.710s	59.487us	1	1	100.00
V2	line_loopback	uart_loopback	0.710s	59.487us	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	17.760s	31.738ms	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	47.870s	41.588ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	10.280s	7.555ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	1.740s	2.384ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	12.431m	139.131ms	1	1	100.00
V2	stress_all	uart_stress_all	3.023m	173.190ms	1	1	100.00
V2	alert_test	uart_alert_test	0.810s	58.440us	1	1	100.00
V2	intr_test	uart_intr_test	0.710s	20.831us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.530s	109.171us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.530s	109.171us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.780s	13.360us	1	1	100.00
		uart_csr_rw	0.650s	93.803us	1	1	100.00
		uart_csr_aliasing	0.620s	26.804us	1	1	100.00
		uart_same_csr_outstanding	0.760s	57.580us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.780s	13.360us	1	1	100.00
		uart_csr_rw	0.650s	93.803us	1	1	100.00
		uart_csr_aliasing	0.620s	26.804us	1	1	100.00
		uart_same_csr_outstanding	0.760s	57.580us	1	1	100.00
V2		TOTAL			17	18	94.44
V2S	tl_intg_err	uart_sec_cm	0.830s	37.573us	1	1	100.00
		uart_tl_intg_err	1.250s	356.363us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.250s	356.363us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	50.820s	12.120ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	27	96.30

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:377) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * has 1 failures:
  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.97112750720277381677058463180888313719164571419753684537532974077750815649327
      Line 74, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @ 31320038784 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 31320038784 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 31320038784 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
        UVM_ERROR @ 31330278784 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 31330618784 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0