CHIP Simulation Results

Wednesday September 03 2025 16:00:25 UTC

GitHub Revision: `83b8114`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	1.396m	2.053ms	1	1	100.00
		chip_sw_example_rom	1.163m	2.194ms	1	1	100.00
		chip_sw_example_manufacturer	2.968m	3.178ms	1	1	100.00
		chip_sw_example_concurrency	2.642m	3.556ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	3.525m	6.615ms	1	1	100.00
V1	csr_rw	chip_csr_rw	6.438m	6.101ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	3.931m	4.294ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	1.017h	29.795ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	44.520s	2.347ms	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	1.017h	29.795ms	1	1	100.00
		chip_csr_rw	6.438m	6.101ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	5.910s	200.147us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	4.318m	3.401ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	4.318m	3.401ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	4.318m	3.401ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	5.366m	4.059ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	5.366m	4.059ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	5.977m	3.804ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	6.240m	4.250ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	6.689m	4.774ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	16.980m	7.431ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	6.955m	4.458ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	18.159m	12.890ms	1	1	100.00
V1		TOTAL			17	18	94.44
V2	chip_pin_mux	chip_padctrl_attributes	2.924m	4.772ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.924m	4.772ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	3.485m	3.556ms	0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	3.555m	5.055ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	3.224m	3.841ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	3.817m	4.136ms	1	1	100.00
		chip_tap_straps_testunlock0	4.247m	5.287ms	1	1	100.00
		chip_tap_straps_rma	2.398m	2.882ms	1	1	100.00
		chip_tap_straps_prod	17.234m	16.072ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	3.231m	2.752ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	11.882m	8.810ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	6.100m	5.042ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	6.100m	5.042ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	8.627m	7.501ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	25.919m	18.903ms	1	1	100.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	6.556m	4.650ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	8.852m	5.539ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	54.608m	18.057ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.367m	2.860ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	9.485m	5.846ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.306m	2.549ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	11.045m	7.081ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.100m	2.545ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.053m	4.559ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.659m	2.953ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	3.056m	3.138ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	3.694m	4.258ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.883m	5.808ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	2.748m	3.135ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.883m	5.808ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	2.018m	2.058ms	1	1	100.00
		chip_sw_aes_smoketest	2.376m	2.248ms	1	1	100.00
		chip_sw_aon_timer_smoketest	2.615m	2.788ms	1	1	100.00
		chip_sw_clkmgr_smoketest	2.934m	3.544ms	1	1	100.00
		chip_sw_csrng_smoketest	2.560m	2.695ms	1	1	100.00
		chip_sw_entropy_src_smoketest	13.625m	6.646ms	1	1	100.00
		chip_sw_gpio_smoketest	2.730m	2.826ms	1	1	100.00
		chip_sw_hmac_smoketest	2.998m	3.142ms	1	1	100.00
		chip_sw_kmac_smoketest	3.226m	3.189ms	1	1	100.00
		chip_sw_otbn_smoketest	16.678m	8.980ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.130m	5.806ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	3.342m	4.916ms	1	1	100.00
		chip_sw_rv_plic_smoketest	2.654m	2.606ms	1	1	100.00
		chip_sw_rv_timer_smoketest	2.841m	2.404ms	1	1	100.00
		chip_sw_rstmgr_smoketest	2.807m	2.880ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	2.550m	3.286ms	1	1	100.00
		chip_sw_uart_smoketest	1.779m	2.904ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	2.797m	2.722ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	5.645m	4.326ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	2.189h	61.173ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	42.035m	14.424ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	2.873m	6.123ms	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	3.019m	3.122ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	3.029m	3.039ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.990h	55.022ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	2.068h	57.057ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	40.220s	1.817ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	40.220s	1.817ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	1.017h	29.795ms	1	1	100.00
		chip_same_csr_outstanding	55.044m	30.117ms	1	1	100.00
		chip_csr_hw_reset	3.525m	6.615ms	1	1	100.00
		chip_csr_rw	6.438m	6.101ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	1.017h	29.795ms	1	1	100.00
		chip_same_csr_outstanding	55.044m	30.117ms	1	1	100.00
		chip_csr_hw_reset	3.525m	6.615ms	1	1	100.00
		chip_csr_rw	6.438m	6.101ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	8.750s	122.057us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	5.620s	56.664us	1	1	100.00
		xbar_smoke_large_delays	1.001m	9.697ms	1	1	100.00
		xbar_smoke_slow_rsp	58.280s	6.516ms	1	1	100.00
		xbar_random_zero_delays	25.180s	440.995us	1	1	100.00
		xbar_random_large_delays	4.378m	42.647ms	1	1	100.00
		xbar_random_slow_rsp	1.735m	11.488ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	16.070s	616.617us	1	1	100.00
		xbar_error_and_unmapped_addr	5.570s	145.446us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	11.340s	506.840us	1	1	100.00
		xbar_error_and_unmapped_addr	5.570s	145.446us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	24.740s	562.366us	1	1	100.00
		xbar_access_same_device_slow_rsp	4.827m	31.693ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	6.080s	63.962us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	4.290m	11.247ms	1	1	100.00
		xbar_stress_all_with_error	3.159m	3.752ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	2.255m	1.870ms	1	1	100.00
		xbar_stress_all_with_reset_error	3.555m	4.745ms	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	42.035m	14.424ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	39.135m	27.693ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	41.700m	14.981ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	32.721m	12.706ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	44.045m	15.848ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	42.148m	16.035ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	41.797m	15.704ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	38.867m	15.357ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	16.240s	10.400us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	17.500s	10.220us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	17.290s	10.220us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	17.150s	10.300us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	18.260s	10.220us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	17.980s	10.220us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	18.650s	10.320us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	17.100s	10.300us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	18.000s	10.280us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	19.600s	10.180us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	16.720s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	17.050s	10.120us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	17.500s	10.280us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	17.040s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	18.640s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	18.420s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	18.500s	10.120us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	16.580s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	20.800s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	17.580s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	16.670s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	16.380s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	24.180s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	16.570s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	17.410s	10.380us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	32.449m	14.085ms	1	1	100.00
		rom_e2e_asm_init_dev	42.428m	17.453ms	1	1	100.00
		rom_e2e_asm_init_prod	40.937m	16.981ms	1	1	100.00
		rom_e2e_asm_init_prod_end	40.715m	15.641ms	1	1	100.00
		rom_e2e_asm_init_rma	39.480m	15.000ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	39.648m	14.430ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	39.614m	17.756ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	40.072m	15.567ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	38.314m	15.496ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	47.353m	34.565ms	0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	47.353m	34.565ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.392m	2.659ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.367m	2.860ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	3.018m	3.030ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	1.795m	3.402ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	17.994m	9.351ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	2.382m	2.811ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	4.757m	4.933ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	5.681m	4.487ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	10.716m	5.602ms	1	1	100.00
		chip_plic_all_irqs_10	5.142m	3.890ms	1	1	100.00
		chip_plic_all_irqs_20	6.609m	4.740ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	3.863m	3.668ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	13.881m	9.832ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	3.469m	3.360ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	2.067m	2.434ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	11.850m	10.053ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	17.921m	8.107ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	18.769m	8.901ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	13.411m	7.802ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	2.343h	255.641ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	4.334m	3.951ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	4.130m	5.806ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	4.334m	3.951ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	6.984m	9.503ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	6.984m	9.503ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	4.351m	7.421ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	6.131m	5.024ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	9.884m	5.714ms	1	1	100.00
		chip_sw_aes_idle	1.795m	3.402ms	1	1	100.00
		chip_sw_hmac_enc_idle	2.414m	2.889ms	1	1	100.00
		chip_sw_kmac_idle	2.746m	2.721ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	4.923m	4.203ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	4.072m	5.152ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	4.721m	4.110ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	3.694m	4.546ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	10.879m	8.873ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	6.258m	4.063ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.108m	4.857ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.088m	3.637ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.007m	4.255ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.830m	3.850ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.591m	4.585ms	1	1	100.00
		chip_sw_ast_clk_outputs	8.627m	7.501ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	7.139m	9.223ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.088m	3.637ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.007m	4.255ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	6.556m	4.650ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	8.852m	5.539ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	54.608m	18.057ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.367m	2.860ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	9.485m	5.846ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.306m	2.549ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	11.045m	7.081ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.100m	2.545ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.053m	4.559ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.659m	2.953ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	1.832m	3.097ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	6.173m	4.887ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	9.967m	6.857ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	48.285m	24.330ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	2.609m	2.928ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.281m	2.570ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	16.647m	9.956ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	2.624m	3.232ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	4.351m	3.685ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	19.218m	23.744ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	30.073m	15.413ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	8.627m	7.501ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	6.226m	5.327ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	4.092m	3.155ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	5.681m	4.487ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	17.921m	8.107ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	20.177m	7.685ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	4.795m	5.304ms	1	1	100.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	6.633m	6.334ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	2.571m	3.302ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	45.394m	16.370ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	1.723m	2.309ms	1	1	100.00
		chip_sw_edn_entropy_reqs	14.400m	7.524ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	1.723m	2.309ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	20.177m	7.685ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	2.437m	2.821ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	21.954m	21.241ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	9.430m	5.308ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	8.852m	5.539ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	4.763m	3.689ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	6.556m	4.650ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	58.415m	44.166ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	21.954m	21.241ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	3.553m	3.598ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	19.194m	10.062ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	3.428m	4.356ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	58.415m	44.166ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	3.428m	4.356ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	3.428m	4.356ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	3.428m	4.356ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	3.428m	4.356ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	5.681m	4.487ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	1.498m	4.666ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	8.723m	4.903ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	7.451m	4.788ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	7.451m	4.788ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	1.916m	2.846ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.306m	2.549ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	2.414m	2.889ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	2.254m	2.637ms	0	1	0.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	5.448m	3.308ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	6.013m	5.303ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	6.557m	4.573ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	6.449m	5.097ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	4.212m	4.241ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	19.194m	10.062ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	11.045m	7.081ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	29.223m	12.276ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	17.994m	9.351ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	40.586m	14.968ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	2.169m	3.392ms	1	1	100.00
		chip_sw_kmac_mode_kmac	2.643m	3.349ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.100m	2.545ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	19.194m	10.062ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	4.543m	6.168ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	2.846m	2.427ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	16.367m	7.479ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	2.746m	2.721ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	4.757m	4.933ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	3.817m	4.136ms	1	1	100.00
		chip_tap_straps_rma	2.398m	2.882ms	1	1	100.00
		chip_tap_straps_prod	17.234m	16.072ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.793m	3.247ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	4.543m	6.168ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	4.543m	6.168ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	4.543m	6.168ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	25.296m	12.731ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	3.428m	4.356ms	1	1	100.00
		chip_sw_flash_rma_unlocked	58.415m	44.166ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	2.930m	3.406ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	8.739m	5.716ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	7.761m	6.092ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	8.503m	6.702ms	1	1	100.00
		chip_sw_lc_ctrl_transition	4.543m	6.168ms	1	1	100.00
		chip_sw_keymgr_key_derivation	19.194m	10.062ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	5.467m	8.630ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	6.121m	7.729ms	1	1	100.00
		chip_prim_tl_access	1.498m	4.666ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	7.139m	9.223ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	6.258m	4.063ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.108m	4.857ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.088m	3.637ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.007m	4.255ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.830m	3.850ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.591m	4.585ms	1	1	100.00
		chip_tap_straps_dev	3.817m	4.136ms	1	1	100.00
		chip_tap_straps_rma	2.398m	2.882ms	1	1	100.00
		chip_tap_straps_prod	17.234m	16.072ms	1	1	100.00
		chip_rv_dm_lc_disabled	9.250m	20.348ms	1	1	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	3.412m	4.200ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.649m	2.710ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.566m	3.041ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	2.681m	4.019ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	24.080m	25.134ms	1	1	100.00
		chip_rv_dm_lc_disabled	9.250m	20.348ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.078h	50.310ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	1.040h	50.718ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	8.867m	8.194ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	1.063h	45.609ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	24.080m	25.134ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.349m	3.181ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.102m	2.235ms	1	1	100.00
		rom_volatile_raw_unlock	1.334m	2.327ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	54.837m	16.511ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	54.608m	18.057ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	9.884m	5.714ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	9.884m	5.714ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	9.884m	5.714ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	4.393m	3.129ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	4.543m	6.168ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	21.954m	21.241ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.393m	3.129ms	1	1	100.00
		chip_sw_keymgr_key_derivation	19.194m	10.062ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	5.193m	4.134ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.949m	2.140ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	21.954m	21.241ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.393m	3.129ms	1	1	100.00
		chip_sw_keymgr_key_derivation	19.194m	10.062ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	5.193m	4.134ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.949m	2.140ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	4.543m	6.168ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	6.248m	5.443ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.793m	3.247ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	2.930m	3.406ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	8.739m	5.716ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	7.761m	6.092ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	8.503m	6.702ms	1	1	100.00
		chip_sw_lc_ctrl_transition	4.543m	6.168ms	1	1	100.00
		chip_prim_tl_access	1.498m	4.666ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	1.498m	4.666ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	17.908m	9.441ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	6.234m	7.538ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	20.768m	27.441ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	4.149m	7.622ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	4.915m	7.208ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	7.080m	6.390ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	17.574m	24.845ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	12.405m	15.195ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	6.984m	9.503ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	11.992m	9.897ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	6.314m	5.683ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	6.234m	7.538ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	3.033m	3.926ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	38.303m	27.832ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	4.531m	5.755ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	3.335m	4.299ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	27.658m	22.435ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	9.622m	7.368ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	14.976m	10.412ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	20.195m	22.680ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	3.067m	3.243ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	5.681m	4.487ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	5.467m	8.630ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	5.467m	8.630ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	14.976m	10.412ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	27.658m	22.435ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	6.314m	5.683ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.130m	5.806ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	2.936m	4.064ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	3.099m	3.586ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	4.425m	4.922ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	13.881m	9.832ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	2.902m	3.200ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	5.681m	4.487ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	18.769m	8.901ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	8.207m	4.441ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	7.693m	4.280ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	3.334m	3.285ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	2.949m	2.140ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	3.099m	3.586ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	3.099m	3.586ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	3.546m	4.547ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	14.773m	13.326ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	2.936m	4.064ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	3.351m	4.142ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	4.835m	5.901ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	2.398m	2.882ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	9.250m	20.348ms	1	1	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	10.716m	5.602ms	1	1	100.00
		chip_plic_all_irqs_10	5.142m	3.890ms	1	1	100.00
		chip_plic_all_irqs_20	6.609m	4.740ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	1.945m	2.715ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	2.591m	2.862ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	42.035m	14.424ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	6.436m	6.180ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	3.144m	2.760ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	3.701m	3.446ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	3.191m	2.726ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	5.193m	4.134ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.053m	4.559ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	7.542m	7.913ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	6.966m	7.658ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	6.121m	7.729ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	5.681m	4.487ms	1	1	100.00
		chip_sw_data_integrity_escalation	6.100m	5.042ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	9.622m	7.368ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	15.899m	23.892ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	3.211m	3.754ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	3.704m	3.856ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	4.838m	4.397ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	15.899m	23.892ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	15.899m	23.892ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	11.228m	11.173ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	11.228m	11.173ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	5.644m	5.547ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	47.353m	34.565ms	0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	1.977m	3.195ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	1.746m	2.332ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	4.546m	3.600ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	5.013m	4.058ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	16.671m	7.452ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.375h	31.397ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	31.184m	12.387ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	2.980m	3.134ms	1	1	100.00
V2		TOTAL			239	275	86.91
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	2.794m	2.930ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	1.850m	2.793ms	0	1	0.00
V2S		TOTAL			1	2	50.00
V3	chip_sw_coremark	chip_sw_coremark	2.615h	72.232ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	6.861m	3.989ms	0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	2.492m	4.513ms	0	1	0.00
		rom_e2e_jtag_debug_dev	19.070m	10.576ms	1	1	100.00
		rom_e2e_jtag_debug_rma	20.409m	12.010ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	2.603m	4.381ms	1	1	100.00
		rom_e2e_jtag_inject_dev	2.992m	4.519ms	1	1	100.00
		rom_e2e_jtag_inject_rma	2.744m	3.271ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	11.063s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	7.811m	4.952ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	4.623m	2.505ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	8.270m	4.013ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	11.036m	6.459ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.476m	2.206ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	9.652m	5.709ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	2.128m	2.757ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	6.344m	4.922ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	3.990m	4.777ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	5.081m	5.150ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	14.976m	10.412ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	2.492m	4.513ms	0	1	0.00
		rom_e2e_jtag_debug_dev	19.070m	10.576ms	1	1	100.00
		rom_e2e_jtag_debug_rma	20.409m	12.010ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	5.085m	5.408ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	5.681m	4.487ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.475h	38.691ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.475h	38.691ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	2.603m	3.449ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	5.366m	4.059ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	50.231m	18.437ms	1	1	100.00
V3		TOTAL			20	23	86.96
	Unmapped tests	chip_sival_flash_info_access	2.844m	3.077ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	6.659m	4.742ms	1	1	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	2.611m	3.190ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	3.573m	3.038ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	4.202m	4.153ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	14.027s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	3.088m	3.487ms	1	1	100.00
		TOTAL			283	325	87.08

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.64806252656574967187368227768408408286774188977427262182475741775629818907982
    Line 472, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.49439151215180120776771839332805061134840258856802457213724029981010975246378
    Line 465, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.48377339066030561299332954254352244154869344256679787029042063839785227153945
    Line 483, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.67615929644077692205368024387225813117859056257534139932904206881258098862891
    Line 506, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.72773184875802558300113974032603809233568107178668189725279574070950770471314
    Line 506, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.111942327266568974543489363842316475492756312280225063118547456602868557450742
    Line 468, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.44309369568420197893947085911833282398671139618225415740048242191892078083160
    Line 467, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.2906241599136420906223257605586153081115271609257433137707117946878969420063
    Line 481, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.7432048081755411274996030934338787822666611070353134040179528227370625205086
    Line 497, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.50082897488392893111517489549091266472500356321831755945288018179738670706432
    Line 491, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.15715291987411127466709469863129861124545009564216710399438168162463433271985
    Line 540, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.22636532904116476460155750816319260917201560367583871800412582575548041013887
    Line 508, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.52855533032543954771837275507649182160521428670467975689181607641741171646342
    Line 503, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.48294440422127176277126557377836605063640319261664606229785096379876151571133
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.176s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.112284344748771995527223515440853137261305931706422867803162044053901628786259
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 0.146s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.71192610624402324473272837444041915453784862571877402334689758466593844696950
    Line 530, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.111915271633511690890921005206539218624827448634006710083056918388500867138906
    Line 495, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.107251789959362402855952906905344506327684166716727251867084062553194417617517
    Line 516, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.17078702698942555516013741913467566644408079772913073449497052526283739869953
    Line 490, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [*] vs *xz [z]) for MIO[*] has 1 failures:
- Test chip_sw_sleep_pin_mio_dio_val has 1 failures.
  - 0.chip_sw_sleep_pin_mio_dio_val.14216565879876091432719158861164811983016844786469932733249179289712825806497
    Line 568, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_pin_mio_dio_val/latest/run.log
```
  UVM_ERROR @ 3555.830000 us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (0x0 [0] vs 0xz [z]) for MIO[30]
  UVM_INFO @ 3555.830000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.2761200739557892232693945254230479753559637725291664940213400630879900890113
    Line 398, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 2760.366670 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 2760.366670 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@78500) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.81053649645534264649612200541191378605519792923897841113361103748020257382027
Line 410, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 3585.686612 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@78500) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h1  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3585.686612 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:200)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor has 1 failures:
- Test chip_sw_sysrst_ctrl_ec_rst_l has 1 failures.
  - 0.chip_sw_sysrst_ctrl_ec_rst_l.113865841223387898754571043525424481519290704680024379769487093533713535467603
    Line 398, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_ec_rst_l/latest/run.log
```
  UVM_ERROR @ 11173.090273 us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:200)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor
  UVM_INFO @ 11173.090273 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 1 failures.
  - 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.96932517999621840782463281190171337626809441645877110664224326126137947098384
    Line 416, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  UVM_ERROR @ 34564.568602 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 34564.568602 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.112922518730591488514057118954530895933005642421734022517450234288519928344277
    Line 393, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 2811.394017 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 42!
  UVM_INFO @ 2811.394017 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.77064537898916922290930814799633920960794554586163399550152572379132621120119
    Line 393, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 2434.276968 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 2434.276968 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: *. has 1 failures:
- Test chip_sw_hmac_oneshot has 1 failures.
  - 0.chip_sw_hmac_oneshot.66373419603402936828359355631832295089443745983885445002666856466627316714471
    Line 397, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_oneshot/latest/run.log
```
  UVM_ERROR @ 2637.264003 us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: 8000534a.
  UVM_INFO @ 2637.264003 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32124) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.44651069214075410689996600029567244745464805722161076158040381328025664002853
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 1816.735080 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32124) { a_addr: 'h10408  a_data: 'hda06ce87  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h7  a_opcode: 'h4  a_user: 'h18108  d_param: 'h0  d_source: 'h7  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 1816.735080 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. has 1 failures:
- Test chip_sw_rv_core_ibex_lockstep_glitch has 1 failures.
  - 0.chip_sw_rv_core_ibex_lockstep_glitch.6560773882174393835514093479638396786499543485645194128926570410953983923963
    Line 404, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
```
  UVM_FATAL @ 2793.255476 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
  UVM_INFO @ 2793.255476 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.74137249785387871420906233784644433976418944596492427532938553367754018005600
    Line 389, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 3121.682000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3121.682000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.100520121916850576064350503026936280937958510379666649312601390868047003980455
    Line 410, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 3039.157000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3039.157000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:196) [chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= * (* [*] vs * [*]) has 1 failures:
- Test chip_sw_power_virus has 1 failures.
  - 0.chip_sw_power_virus.106506187800985117069302478856283410391503072058355212532215305420518218794977
    Line 451, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 3989.023202 us: (chip_sw_power_virus_vseq.sv:196) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 3989.023202 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.57935932455510093831909459077557639935734352674479520370098517128326161282414
    Line 495, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.109622392985555187300491393500331310636827660839796976340184058677446969633963
    Line 501, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (jtag_rv_debugger.sv:784) [debugger] Index * appears to be out of bounds has 1 failures:
- Test rom_e2e_jtag_debug_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_debug_test_unlocked0.66418123316828332108938076619715837053457146386037489092917281130180922936205
    Line 455, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log
```
  UVM_ERROR @ 4512.904858 us: (jtag_rv_debugger.sv:784) [debugger] Index 3 appears to be out of bounds
  UVM_INFO @ 4512.904858 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31954) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

0.chip_csr_mem_rw_with_rand_reset.11100831845790884725131552005899829650741208048081100568294267286918500844541
Line 221, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2347.428528 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31954) { a_addr: 'h1071c  a_data: 'hc55e30e2  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h28  a_opcode: 'h4  a_user: 'h1a518  d_param: 'h0  d_source: 'h28  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2347.428528 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---