EDN Simulation Results

Thursday September 04 2025 19:17:11 UTC

GitHub Revision: e649bd3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	0.900s	55.649us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.780s	21.818us	1	1	100.00
V1	csr_rw	edn_csr_rw	0.870s	13.037us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	2.240s	96.041us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	1.010s	218.106us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.360s	30.060us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.870s	13.037us	1	1	100.00
		edn_csr_aliasing	1.010s	218.106us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	1.000s	26.676us	1	1	100.00
V2	csrng_commands	edn_genbits	1.000s	26.676us	1	1	100.00
V2	genbits	edn_genbits	1.000s	26.676us	1	1	100.00
V2	interrupts	edn_intr	0.880s	20.971us	1	1	100.00
V2	alerts	edn_alert	1.170s	89.309us	1	1	100.00
V2	errs	edn_err	1.000s	24.487us	1	1	100.00
V2	disable	edn_disable	0.960s	14.236us	1	1	100.00
		edn_disable_auto_req_mode	1.040s	29.742us	1	1	100.00
V2	stress_all	edn_stress_all	4.450s	330.180us	1	1	100.00
V2	intr_test	edn_intr_test	0.830s	41.933us	1	1	100.00
V2	alert_test	edn_alert_test	0.940s	53.691us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	2.120s	164.075us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	2.120s	164.075us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.780s	21.818us	1	1	100.00
		edn_csr_rw	0.870s	13.037us	1	1	100.00
		edn_csr_aliasing	1.010s	218.106us	1	1	100.00
		edn_same_csr_outstanding	1.370s	101.876us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.780s	21.818us	1	1	100.00
		edn_csr_rw	0.870s	13.037us	1	1	100.00
		edn_csr_aliasing	1.010s	218.106us	1	1	100.00
		edn_same_csr_outstanding	1.370s	101.876us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	3.240s	645.996us	1	1	100.00
		edn_tl_intg_err	1.750s	240.422us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	0.810s	18.297us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	1.170s	89.309us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	3.240s	645.996us	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	3.240s	645.996us	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	3.240s	645.996us	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	3.240s	645.996us	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.170s	89.309us	1	1	100.00
		edn_sec_cm	3.240s	645.996us	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.170s	89.309us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	1.750s	240.422us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	53.500s	6.431ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00