HMAC Simulation Results

Thursday September 04 2025 19:17:11 UTC

GitHub Revision: e649bd3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 5.650s 434.744us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.130s 143.550us 1 1 100.00
V1 csr_rw hmac_csr_rw 0.910s 86.484us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 7.350s 2.826ms 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 4.530s 1.341ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 11.392m 351.246ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 0.910s 86.484us 1 1 100.00
hmac_csr_aliasing 4.530s 1.341ms 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 30.480s 12.040ms 1 1 100.00
V2 back_pressure hmac_back_pressure 46.150s 4.078ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 7.930s 593.690us 1 1 100.00
hmac_test_sha384_vectors 5.884m 37.354ms 1 1 100.00
hmac_test_sha512_vectors 19.820s 218.924us 1 1 100.00
hmac_test_hmac256_vectors 9.060s 303.127us 1 1 100.00
hmac_test_hmac384_vectors 8.460s 1.085ms 1 1 100.00
hmac_test_hmac512_vectors 6.480s 361.202us 1 1 100.00
V2 burst_wr hmac_burst_wr 2.660s 364.177us 1 1 100.00
V2 datapath_stress hmac_datapath_stress 1.669m 765.526us 1 1 100.00
V2 error hmac_error 3.380s 469.071us 1 1 100.00
V2 wipe_secret hmac_wipe_secret 5.340s 265.625us 1 1 100.00
V2 save_and_restore hmac_smoke 5.650s 434.744us 1 1 100.00
hmac_long_msg 30.480s 12.040ms 1 1 100.00
hmac_back_pressure 46.150s 4.078ms 1 1 100.00
hmac_datapath_stress 1.669m 765.526us 1 1 100.00
hmac_burst_wr 2.660s 364.177us 1 1 100.00
hmac_stress_all 10.607m 11.261ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 5.650s 434.744us 1 1 100.00
hmac_long_msg 30.480s 12.040ms 1 1 100.00
hmac_back_pressure 46.150s 4.078ms 1 1 100.00
hmac_datapath_stress 1.669m 765.526us 1 1 100.00
hmac_wipe_secret 5.340s 265.625us 1 1 100.00
hmac_test_sha256_vectors 7.930s 593.690us 1 1 100.00
hmac_test_sha384_vectors 5.884m 37.354ms 1 1 100.00
hmac_test_sha512_vectors 19.820s 218.924us 1 1 100.00
hmac_test_hmac256_vectors 9.060s 303.127us 1 1 100.00
hmac_test_hmac384_vectors 8.460s 1.085ms 1 1 100.00
hmac_test_hmac512_vectors 6.480s 361.202us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 5.650s 434.744us 1 1 100.00
hmac_long_msg 30.480s 12.040ms 1 1 100.00
hmac_back_pressure 46.150s 4.078ms 1 1 100.00
hmac_datapath_stress 1.669m 765.526us 1 1 100.00
hmac_burst_wr 2.660s 364.177us 1 1 100.00
hmac_error 3.380s 469.071us 1 1 100.00
hmac_wipe_secret 5.340s 265.625us 1 1 100.00
hmac_test_sha256_vectors 7.930s 593.690us 1 1 100.00
hmac_test_sha384_vectors 5.884m 37.354ms 1 1 100.00
hmac_test_sha512_vectors 19.820s 218.924us 1 1 100.00
hmac_test_hmac256_vectors 9.060s 303.127us 1 1 100.00
hmac_test_hmac384_vectors 8.460s 1.085ms 1 1 100.00
hmac_test_hmac512_vectors 6.480s 361.202us 1 1 100.00
hmac_stress_all 10.607m 11.261ms 1 1 100.00
V2 stress_all hmac_stress_all 10.607m 11.261ms 1 1 100.00
V2 alert_test hmac_alert_test 0.700s 41.236us 1 1 100.00
V2 intr_test hmac_intr_test 0.820s 36.773us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.820s 1.224ms 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.820s 1.224ms 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.130s 143.550us 1 1 100.00
hmac_csr_rw 0.910s 86.484us 1 1 100.00
hmac_csr_aliasing 4.530s 1.341ms 1 1 100.00
hmac_same_csr_outstanding 1.570s 82.196us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.130s 143.550us 1 1 100.00
hmac_csr_rw 0.910s 86.484us 1 1 100.00
hmac_csr_aliasing 4.530s 1.341ms 1 1 100.00
hmac_same_csr_outstanding 1.570s 82.196us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 0.970s 355.931us 1 1 100.00
hmac_tl_intg_err 2.170s 328.633us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 2.170s 328.633us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 5.650s 434.744us 1 1 100.00
V3 stress_reset hmac_stress_reset 2.750s 351.850us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 8.120m 152.147ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 1.810s 382.432us 1 1 100.00
TOTAL 28 28 100.00