I2C Simulation Results

Thursday September 04 2025 19:17:11 UTC

GitHub Revision: e649bd3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	13.330s	1.038ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	10.970s	886.209us	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.970s	26.666us	1	1	100.00
V1	csr_rw	i2c_csr_rw	0.750s	69.531us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	2.420s	282.047us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.780s	97.521us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.020s	32.929us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.750s	69.531us	1	1	100.00
		i2c_csr_aliasing	1.780s	97.521us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	1.080s	120.852us	0	1	0.00
V2	host_stress_all	i2c_host_stress_all	4.005m	186.889ms	1	1	100.00
V2	host_maxperf	i2c_host_perf	26.160s	6.937ms	1	1	100.00
V2	host_override	i2c_host_override	0.780s	278.562us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	2.553m	3.791ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	1.732m	2.291ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.390s	544.388us	1	1	100.00
		i2c_host_fifo_fmt_empty	6.610s	1.620ms	1	1	100.00
		i2c_host_fifo_reset_rx	5.400s	448.943us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	42.730s	4.615ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	15.420s	1.134ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.810s	431.590us	1	1	100.00
V2	target_glitch	i2c_target_glitch	3.220s	519.893us	0	1	0.00
V2	target_stress_all	i2c_target_stress_all	23.080s	26.168ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	3.130s	1.386ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	5.800s	450.253us	1	1	100.00
		i2c_target_intr_smoke	2.900s	2.932ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	0.880s	469.640us	1	1	100.00
		i2c_target_fifo_reset_tx	1.110s	173.290us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	16.660s	16.490ms	1	1	100.00
		i2c_target_stress_rd	5.800s	450.253us	1	1	100.00
		i2c_target_intr_stress_wr	58.660s	14.035ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.610s	1.172ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	6.050s	2.293ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	3.550s	912.205us	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	4.790s	10.180ms	0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.960s	2.596ms	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.040s	584.156us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	26.160s	6.937ms	1	1	100.00
		i2c_host_perf_precise	2.890s	438.990us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	15.420s	1.134ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	0.710s	2.004us	0	1	0.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.290s	524.654us	1	1	100.00
		i2c_target_nack_acqfull_addr	1.770s	1.809ms	1	1	100.00
		i2c_target_nack_txstretch	1.220s	1.380ms	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	12.310s	423.308us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	1.540s	455.803us	1	1	100.00
V2	alert_test	i2c_alert_test	0.700s	16.242us	1	1	100.00
V2	intr_test	i2c_intr_test	0.890s	17.420us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.330s	630.667us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.330s	630.667us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.970s	26.666us	1	1	100.00
		i2c_csr_rw	0.750s	69.531us	1	1	100.00
		i2c_csr_aliasing	1.780s	97.521us	1	1	100.00
		i2c_same_csr_outstanding	1.190s	113.100us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.970s	26.666us	1	1	100.00
		i2c_csr_rw	0.750s	69.531us	1	1	100.00
		i2c_csr_aliasing	1.780s	97.521us	1	1	100.00
		i2c_same_csr_outstanding	1.190s	113.100us	1	1	100.00
V2		TOTAL			34	38	89.47
V2S	tl_intg_err	i2c_tl_intg_err	1.740s	130.735us	1	1	100.00
		i2c_sec_cm	1.270s	133.780us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.740s	130.735us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	44.050s	4.668ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	0.910s	272.802us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	10.400s	4.372ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			43	50	86.00

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:945) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.6081139676953148206091758650172998413048728989540675651862174722205832059828
      Line 104, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4667516681 ps: (cip_base_vseq.sv:945) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 4667516681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.9642796322542771554748344185234893839183963609173265830114057972211847341352
      Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4371754608 ps: (cip_base_vseq.sv:945) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 4371754608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_host_error_intr has 1 failures.

    • 0.i2c_host_error_intr.54803782386269716080213071609816714443251749547840628084392847009861853528272
      Line 91, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

        UVM_ERROR @ 120851638 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @ 120851638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_target_glitch has 1 failures.

    • 0.i2c_target_glitch.5071952700435801626371438656566918921364071180923574812036044149836911654238
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

        UVM_ERROR @ 519893481 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
        UVM_INFO @ 519893481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.1133947404092990160510934320790748272709840094246521293890031582293797512519
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @ 272801891 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 272801891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:

  • Test i2c_target_hrst has 1 failures.

    • 0.i2c_target_hrst.64085431400406506996893363478476186942340345997744552312624551365889499422024
      Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log

        UVM_FATAL @ 10179734939 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
        UVM_INFO @ 10179734939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:

  • Test i2c_target_tx_stretch_ctrl has 1 failures.

    • 0.i2c_target_tx_stretch_ctrl.44863182314727055288688093548513693870242420149460090632467338047954438082431
      Line 121, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_tx_stretch_ctrl/latest/run.log

        Error-[CNST-CIF] Constraints inconsistency failure
        src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
          Constraints are inconsistent and cannot be solved.
          Please check the inconsistent constraints being printed above and rewrite
          them.