| V1 |
smoke |
kmac_smoke |
10.800s |
572.505us |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
kmac_csr_hw_reset |
1.370s |
35.534us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
kmac_csr_rw |
1.070s |
22.022us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
kmac_csr_bit_bash |
13.910s |
1.441ms |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
kmac_csr_aliasing |
3.710s |
512.345us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
kmac_csr_mem_rw_with_rand_reset |
2.650s |
334.349us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
kmac_csr_rw |
1.070s |
22.022us |
1 |
1 |
100.00 |
|
|
kmac_csr_aliasing |
3.710s |
512.345us |
1 |
1 |
100.00 |
| V1 |
mem_walk |
kmac_mem_walk |
0.990s |
48.104us |
1 |
1 |
100.00 |
| V1 |
mem_partial_access |
kmac_mem_partial_access |
1.130s |
32.100us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
8 |
8 |
100.00 |
| V2 |
long_msg_and_output |
kmac_long_msg_and_output |
34.703m |
55.732ms |
1 |
1 |
100.00 |
| V2 |
burst_write |
kmac_burst_write |
8.053m |
18.744ms |
1 |
1 |
100.00 |
| V2 |
test_vectors |
kmac_test_vectors_sha3_224 |
26.005m |
128.821ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_sha3_256 |
29.259m |
347.724ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_sha3_384 |
19.505m |
91.863ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_sha3_512 |
13.520s |
5.218ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_shake_128 |
37.992m |
593.205ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_shake_256 |
1.548m |
4.766ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_kmac |
2.330s |
310.254us |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_kmac_xof |
2.290s |
159.802us |
1 |
1 |
100.00 |
| V2 |
sideload |
kmac_sideload |
4.990m |
29.283ms |
1 |
1 |
100.00 |
| V2 |
app |
kmac_app |
1.619m |
10.584ms |
1 |
1 |
100.00 |
| V2 |
app_with_partial_data |
kmac_app_with_partial_data |
2.995m |
13.891ms |
1 |
1 |
100.00 |
| V2 |
entropy_refresh |
kmac_entropy_refresh |
19.290s |
945.478us |
1 |
1 |
100.00 |
| V2 |
error |
kmac_error |
17.600s |
1.180ms |
1 |
1 |
100.00 |
| V2 |
key_error |
kmac_key_error |
1.820s |
1.157ms |
1 |
1 |
100.00 |
| V2 |
sideload_invalid |
kmac_sideload_invalid |
1.220s |
65.843us |
1 |
1 |
100.00 |
| V2 |
edn_timeout_error |
kmac_edn_timeout_error |
30.670s |
7.603ms |
1 |
1 |
100.00 |
| V2 |
entropy_mode_error |
kmac_entropy_mode_error |
11.550s |
602.246us |
1 |
1 |
100.00 |
| V2 |
entropy_ready_error |
kmac_entropy_ready_error |
45.400s |
6.768ms |
1 |
1 |
100.00 |
| V2 |
lc_escalation |
kmac_lc_escalation |
1.350s |
28.291us |
1 |
1 |
100.00 |
| V2 |
stress_all |
kmac_stress_all |
3.087m |
9.903ms |
1 |
1 |
100.00 |
| V2 |
intr_test |
kmac_intr_test |
0.860s |
12.445us |
1 |
1 |
100.00 |
| V2 |
alert_test |
kmac_alert_test |
0.910s |
32.998us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
kmac_tl_errors |
2.960s |
228.991us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
kmac_tl_errors |
2.960s |
228.991us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
kmac_csr_hw_reset |
1.370s |
35.534us |
1 |
1 |
100.00 |
|
|
kmac_csr_rw |
1.070s |
22.022us |
1 |
1 |
100.00 |
|
|
kmac_csr_aliasing |
3.710s |
512.345us |
1 |
1 |
100.00 |
|
|
kmac_same_csr_outstanding |
2.280s |
41.783us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
kmac_csr_hw_reset |
1.370s |
35.534us |
1 |
1 |
100.00 |
|
|
kmac_csr_rw |
1.070s |
22.022us |
1 |
1 |
100.00 |
|
|
kmac_csr_aliasing |
3.710s |
512.345us |
1 |
1 |
100.00 |
|
|
kmac_same_csr_outstanding |
2.280s |
41.783us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
26 |
26 |
100.00 |
| V2S |
shadow_reg_update_error |
kmac_shadow_reg_errors |
1.970s |
98.637us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_read_clear_staged_value |
kmac_shadow_reg_errors |
1.970s |
98.637us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_storage_error |
kmac_shadow_reg_errors |
1.970s |
98.637us |
1 |
1 |
100.00 |
| V2S |
shadowed_reset_glitch |
kmac_shadow_reg_errors |
1.970s |
98.637us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error_with_csr_rw |
kmac_shadow_reg_errors_with_csr_rw |
4.330s |
164.820us |
1 |
1 |
100.00 |
| V2S |
tl_intg_err |
kmac_sec_cm |
41.690s |
5.948ms |
1 |
1 |
100.00 |
|
|
kmac_tl_intg_err |
3.360s |
195.050us |
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
kmac_tl_intg_err |
3.360s |
195.050us |
1 |
1 |
100.00 |
| V2S |
sec_cm_lc_escalate_en_intersig_mubi |
kmac_lc_escalation |
1.350s |
28.291us |
1 |
1 |
100.00 |
| V2S |
sec_cm_sw_key_key_masking |
kmac_smoke |
10.800s |
572.505us |
1 |
1 |
100.00 |
| V2S |
sec_cm_key_sideload |
kmac_sideload |
4.990m |
29.283ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_cfg_shadowed_config_shadow |
kmac_shadow_reg_errors |
1.970s |
98.637us |
1 |
1 |
100.00 |
| V2S |
sec_cm_fsm_sparse |
kmac_sec_cm |
41.690s |
5.948ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_ctr_redun |
kmac_sec_cm |
41.690s |
5.948ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_packer_ctr_redun |
kmac_sec_cm |
41.690s |
5.948ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_cfg_shadowed_config_regwen |
kmac_smoke |
10.800s |
572.505us |
1 |
1 |
100.00 |
| V2S |
sec_cm_fsm_global_esc |
kmac_lc_escalation |
1.350s |
28.291us |
1 |
1 |
100.00 |
| V2S |
sec_cm_fsm_local_esc |
kmac_sec_cm |
41.690s |
5.948ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_absorbed_ctrl_mubi |
kmac_mubi |
4.172m |
17.228ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_sw_cmd_ctrl_sparse |
kmac_smoke |
10.800s |
572.505us |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
5 |
5 |
100.00 |
| V3 |
stress_all_with_rand_reset |
kmac_stress_all_with_rand_reset |
1.864m |
5.059ms |
1 |
1 |
100.00 |
| V3 |
|
TOTAL |
|
|
1 |
1 |
100.00 |
|
|
TOTAL |
|
|
40 |
40 |
100.00 |