OTBN Simulation Results

Thursday September 04 2025 19:17:11 UTC

GitHub Revision: e649bd3

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	12.000s	115.444us	1	1	100.00
V1	single_binary	otbn_single	7.000s	104.626us	1	1	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	5.000s	19.995us	1	1	100.00
V1	csr_rw	otbn_csr_rw	8.000s	16.459us	1	1	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	6.000s	154.662us	1	1	100.00
V1	csr_aliasing	otbn_csr_aliasing	5.000s	20.626us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	9.000s	97.194us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	8.000s	16.459us	1	1	100.00
		otbn_csr_aliasing	5.000s	20.626us	1	1	100.00
V1	mem_walk	otbn_mem_walk	28.000s	11.159ms	1	1	100.00
V1	mem_partial_access	otbn_mem_partial_access	9.000s	129.902us	1	1	100.00
V1		TOTAL			9	9	100.00
V2	reset_recovery	otbn_reset	19.000s	121.799us	1	1	100.00
V2	multi_error	otbn_multi_err	43.000s	479.122us	1	1	100.00
V2	back_to_back	otbn_multi	33.000s	530.401us	1	1	100.00
V2	stress_all	otbn_stress_all	8.000s	37.755us	1	1	100.00
V2	lc_escalation	otbn_escalate	8.000s	180.981us	1	1	100.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	7.000s	16.189us	1	1	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	19.000s	54.657us	1	1	100.00
V2	alert_test	otbn_alert_test	5.000s	15.333us	1	1	100.00
V2	intr_test	otbn_intr_test	6.000s	72.316us	1	1	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	6.000s	1.010ms	1	1	100.00
V2	tl_d_illegal_access	otbn_tl_errors	6.000s	1.010ms	1	1	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	5.000s	19.995us	1	1	100.00
		otbn_csr_rw	8.000s	16.459us	1	1	100.00
		otbn_csr_aliasing	5.000s	20.626us	1	1	100.00
		otbn_same_csr_outstanding	4.000s	43.915us	1	1	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	5.000s	19.995us	1	1	100.00
		otbn_csr_rw	8.000s	16.459us	1	1	100.00
		otbn_csr_aliasing	5.000s	20.626us	1	1	100.00
		otbn_same_csr_outstanding	4.000s	43.915us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	mem_integrity	otbn_imem_err	8.000s	17.071us	1	1	100.00
		otbn_dmem_err	8.000s	34.011us	1	1	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	10.000s	234.623us	1	1	100.00
		otbn_controller_ispr_rdata_err	10.000s	108.035us	1	1	100.00
		otbn_mac_bignum_acc_err	9.000s	187.229us	1	1	100.00
		otbn_urnd_err	6.000s	30.489us	1	1	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	7.000s	27.006us	1	1	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	13.000s	45.330us	1	1	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	6.000s	21.211us	1	1	100.00
V2S	tl_intg_err	otbn_sec_cm	11.000s	130.294us	0	1	0.00
		otbn_tl_intg_err	13.000s	155.035us	1	1	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	30.000s	216.473us	1	1	100.00
V2S	prim_fsm_check	otbn_sec_cm	11.000s	130.294us	0	1	0.00
V2S	prim_count_check	otbn_sec_cm	11.000s	130.294us	0	1	0.00
V2S	sec_cm_mem_scramble	otbn_smoke	12.000s	115.444us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	8.000s	34.011us	1	1	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	8.000s	17.071us	1	1	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	13.000s	155.035us	1	1	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	8.000s	180.981us	1	1	100.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	8.000s	17.071us	1	1	100.00
		otbn_dmem_err	8.000s	34.011us	1	1	100.00
		otbn_zero_state_err_urnd	7.000s	16.189us	1	1	100.00
		otbn_illegal_mem_acc	7.000s	27.006us	1	1	100.00
		otbn_sec_cm	11.000s	130.294us	0	1	0.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	11.000s	130.294us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	otbn_single	7.000s	104.626us	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	8.000s	17.071us	1	1	100.00
		otbn_dmem_err	8.000s	34.011us	1	1	100.00
		otbn_zero_state_err_urnd	7.000s	16.189us	1	1	100.00
		otbn_illegal_mem_acc	7.000s	27.006us	1	1	100.00
		otbn_sec_cm	11.000s	130.294us	0	1	0.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	11.000s	130.294us	0	1	0.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	8.000s	180.981us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	8.000s	17.071us	1	1	100.00
		otbn_dmem_err	8.000s	34.011us	1	1	100.00
		otbn_zero_state_err_urnd	7.000s	16.189us	1	1	100.00
		otbn_illegal_mem_acc	7.000s	27.006us	1	1	100.00
		otbn_sec_cm	11.000s	130.294us	0	1	0.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	11.000s	130.294us	0	1	0.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	7.000s	104.626us	1	1	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	7.000s	19.954us	1	1	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	7.000s	51.901us	1	1	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	18.000s	410.376us	1	1	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	18.000s	410.376us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	8.000s	20.716us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	11.000s	130.294us	0	1	0.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	11.000s	130.294us	0	1	0.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	7.000s	185.089us	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	11.000s	130.294us	0	1	0.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	11.000s	130.294us	0	1	0.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	8.000s	29.494us	1	1	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	8.000s	29.494us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	6.000s	19.646us	1	1	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	7.000s	104.626us	1	1	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	7.000s	104.626us	1	1	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	7.000s	104.626us	1	1	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	33.000s	530.401us	1	1	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	7.000s	104.626us	1	1	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	7.000s	104.626us	1	1	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	12.000s	33.624us	1	1	100.00
V2S	sec_cm_key_sideload	otbn_single	7.000s	104.626us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	11.000s	130.294us	0	1	0.00
V2S		TOTAL			19	20	95.00
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	1.033m	306.689us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			39	41	95.12

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:946) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test otbn_stress_all_with_rand_reset has 1 failures.

    • 0.otbn_stress_all_with_rand_reset.38164451742997838438646559197547773516140046305293789405277225234622074242309
      Line 218, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 306688775 ps: (cip_base_vseq.sv:946) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 306688775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1386): Assertion ErrBitsKnown_A has failed has 1 failures:

  • Test otbn_sec_cm has 1 failures.

    • 0.otbn_sec_cm.102918237229185973609306525338063691780765246562118623309136021947336943682095
      Line 111, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log

        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1386): (time 130294335 PS) Assertion tb.dut.ErrBitsKnown_A has failed
        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 130294335 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 130294335 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 130294335 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 130294335 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed