PATTGEN Simulation Results

Thursday September 04 2025 19:17:11 UTC

GitHub Revision: `e649bd3`

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	4.000s	144.913us	1	1	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	3.000s	73.960us	1	1	100.00
V1	csr_rw	pattgen_csr_rw	2.000s	49.851us	1	1	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	3.000s	100.498us	1	1	100.00
V1	csr_aliasing	pattgen_csr_aliasing	2.000s	14.701us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	3.000s	27.149us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	2.000s	49.851us	1	1	100.00
		pattgen_csr_aliasing	2.000s	14.701us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	perf	pattgen_perf	18.183m	85.742ms	1	1	100.00
V2	cnt_rollover	cnt_rollover	36.000s	1.332ms	1	1	100.00
V2	error	pattgen_error	3.000s	29.678us	1	1	100.00
V2	stress_all	pattgen_stress_all	3.000s	78.494us	0	1	0.00
V2	alert_test	pattgen_alert_test	2.000s	14.605us	1	1	100.00
V2	intr_test	pattgen_intr_test	3.000s	23.810us	1	1	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	4.000s	69.212us	1	1	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	4.000s	69.212us	1	1	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	3.000s	73.960us	1	1	100.00
		pattgen_csr_rw	2.000s	49.851us	1	1	100.00
		pattgen_csr_aliasing	2.000s	14.701us	1	1	100.00
		pattgen_same_csr_outstanding	3.000s	32.838us	1	1	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	3.000s	73.960us	1	1	100.00
		pattgen_csr_rw	2.000s	49.851us	1	1	100.00
		pattgen_csr_aliasing	2.000s	14.701us	1	1	100.00
		pattgen_same_csr_outstanding	3.000s	32.838us	1	1	100.00
V2		TOTAL			7	8	87.50
V2S	tl_intg_err	pattgen_tl_intg_err	2.000s	146.252us	1	1	100.00
		pattgen_sec_cm	3.000s	594.681us	1	1	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	2.000s	146.252us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	1.050m	20.356ms	0	1	0.00
V3		TOTAL			0	1	0.00
	Unmapped tests	pattgen_inactive_level	3.000s	178.718us	1	1	100.00
		TOTAL			16	18	88.89

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:946) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

Test pattgen_stress_all_with_rand_reset has 1 failures.

0.pattgen_stress_all_with_rand_reset.100686343311476990103805915851036830254262763283338083072219569190359264484688
Line 385, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 15873056209 ps: (cip_base_vseq.sv:946) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 15873063025 ps: (cip_base_vseq.sv:850) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 15873063025 ps: (cip_base_vseq.sv:853) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 6/10
  UVM_INFO @ 15873290300 ps: (cip_base_vseq.sv:874) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: has 1 failures:
- Test pattgen_stress_all has 1 failures.
  - 0.pattgen_stress_all.29531294974435995987614545437816952097236859882886207713873907686055322921040
    Line 158, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all/latest/run.log
```
  UVM_ERROR @  78493917 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
  ------------------------------------
  Name      Type          Size  Value
  ------------------------------------
  exp_item  pattgen_item  -     @10366
```