ROM_CTRL/32KB Simulation Results

Thursday September 04 2025 19:17:11 UTC

GitHub Revision: e649bd3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 5.590s 312.365us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 5.790s 296.315us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 3.210s 502.906us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 4.320s 299.752us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 4.180s 574.426us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 4.450s 449.108us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 3.210s 502.906us 1 1 100.00
rom_ctrl_csr_aliasing 4.180s 574.426us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 5.380s 1.415ms 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 3.860s 296.092us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 4.830s 326.364us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 10.020s 4.812ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 6.600s 396.090us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 4.260s 287.076us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 6.530s 730.331us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 6.530s 730.331us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 5.790s 296.315us 1 1 100.00
rom_ctrl_csr_rw 3.210s 502.906us 1 1 100.00
rom_ctrl_csr_aliasing 4.180s 574.426us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.710s 127.115us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 5.790s 296.315us 1 1 100.00
rom_ctrl_csr_rw 3.210s 502.906us 1 1 100.00
rom_ctrl_csr_aliasing 4.180s 574.426us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.710s 127.115us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 45.040s 2.018ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 12.020s 3.624ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 1.586m 1.078ms 1 1 100.00
rom_ctrl_tl_intg_err 23.450s 751.052us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 1.586m 1.078ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 1.586m 1.078ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 45.040s 2.018ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 45.040s 2.018ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 45.040s 2.018ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 45.040s 2.018ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 45.040s 2.018ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 1.586m 1.078ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 1.586m 1.078ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 5.590s 312.365us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 5.590s 312.365us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 5.590s 312.365us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 23.450s 751.052us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 45.040s 2.018ms 1 1 100.00
rom_ctrl_kmac_err_chk 6.600s 396.090us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 45.040s 2.018ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 45.040s 2.018ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 45.040s 2.018ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 12.020s 3.624ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 1.586m 1.078ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 2.399m 5.095ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00