ROM_CTRL/64KB Simulation Results

Thursday September 04 2025 19:17:11 UTC

GitHub Revision: e649bd3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 9.020s 301.547us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 10.840s 555.165us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 8.000s 291.878us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 9.650s 301.494us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 7.510s 294.622us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 6.580s 736.692us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 8.000s 291.878us 1 1 100.00
rom_ctrl_csr_aliasing 7.510s 294.622us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 7.090s 301.456us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 7.730s 297.983us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 8.730s 723.046us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 22.800s 596.432us 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 12.150s 5.545ms 1 1 100.00
V2 alert_test rom_ctrl_alert_test 7.360s 3.110ms 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 8.450s 546.002us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 8.450s 546.002us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 10.840s 555.165us 1 1 100.00
rom_ctrl_csr_rw 8.000s 291.878us 1 1 100.00
rom_ctrl_csr_aliasing 7.510s 294.622us 1 1 100.00
rom_ctrl_same_csr_outstanding 8.650s 711.058us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 10.840s 555.165us 1 1 100.00
rom_ctrl_csr_rw 8.000s 291.878us 1 1 100.00
rom_ctrl_csr_aliasing 7.510s 294.622us 1 1 100.00
rom_ctrl_same_csr_outstanding 8.650s 711.058us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 1.880m 7.051ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 26.520s 2.066ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 7.023m 956.476us 1 1 100.00
rom_ctrl_tl_intg_err 47.270s 379.146us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 7.023m 956.476us 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 7.023m 956.476us 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.880m 7.051ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.880m 7.051ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.880m 7.051ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.880m 7.051ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.880m 7.051ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 7.023m 956.476us 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 7.023m 956.476us 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 9.020s 301.547us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 9.020s 301.547us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 9.020s 301.547us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 47.270s 379.146us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.880m 7.051ms 1 1 100.00
rom_ctrl_kmac_err_chk 12.150s 5.545ms 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 1.880m 7.051ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 1.880m 7.051ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 1.880m 7.051ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 26.520s 2.066ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 7.023m 956.476us 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 25.650s 910.885us 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00