| V1 |
random |
rv_timer_random |
0.630s |
25.083us |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
rv_timer_csr_hw_reset |
0.670s |
45.172us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
rv_timer_csr_rw |
0.590s |
22.219us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
rv_timer_csr_bit_bash |
2.250s |
86.251us |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
rv_timer_csr_aliasing |
0.740s |
25.894us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
rv_timer_csr_mem_rw_with_rand_reset |
0.940s |
20.954us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
rv_timer_csr_rw |
0.590s |
22.219us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_aliasing |
0.740s |
25.894us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
6 |
6 |
100.00 |
| V2 |
random_reset |
rv_timer_random_reset |
0.630s |
87.844us |
1 |
1 |
100.00 |
| V2 |
disabled |
rv_timer_disabled |
3.150s |
2.174ms |
1 |
1 |
100.00 |
| V2 |
cfg_update_on_fly |
rv_timer_cfg_update_on_fly |
10.530s |
8.339ms |
1 |
1 |
100.00 |
| V2 |
no_interrupt_test |
rv_timer_cfg_update_on_fly |
10.530s |
8.339ms |
1 |
1 |
100.00 |
| V2 |
stress |
rv_timer_stress_all |
2.890s |
1.979ms |
1 |
1 |
100.00 |
| V2 |
alert_test |
rv_timer_alert_test |
0.640s |
17.063us |
1 |
1 |
100.00 |
| V2 |
intr_test |
rv_timer_intr_test |
0.570s |
16.749us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
rv_timer_tl_errors |
2.050s |
647.433us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
rv_timer_tl_errors |
2.050s |
647.433us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
rv_timer_csr_hw_reset |
0.670s |
45.172us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_rw |
0.590s |
22.219us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_aliasing |
0.740s |
25.894us |
1 |
1 |
100.00 |
|
|
rv_timer_same_csr_outstanding |
0.650s |
110.092us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
rv_timer_csr_hw_reset |
0.670s |
45.172us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_rw |
0.590s |
22.219us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_aliasing |
0.740s |
25.894us |
1 |
1 |
100.00 |
|
|
rv_timer_same_csr_outstanding |
0.650s |
110.092us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
8 |
8 |
100.00 |
| V2S |
tl_intg_err |
rv_timer_sec_cm |
1.230s |
356.246us |
1 |
1 |
100.00 |
|
|
rv_timer_tl_intg_err |
1.010s |
301.537us |
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
rv_timer_tl_intg_err |
1.010s |
301.537us |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
2 |
2 |
100.00 |
| V3 |
min_value |
rv_timer_min |
0.600s |
14.145us |
1 |
1 |
100.00 |
| V3 |
max_value |
rv_timer_max |
0.690s |
54.049us |
1 |
1 |
100.00 |
| V3 |
stress_all_with_rand_reset |
rv_timer_stress_all_with_rand_reset |
40.260s |
41.748ms |
1 |
1 |
100.00 |
| V3 |
|
TOTAL |
|
|
3 |
3 |
100.00 |
|
|
TOTAL |
|
|
19 |
19 |
100.00 |