SPI_DEVICE/1R1W Simulation Results

Thursday September 04 2025 19:17:11 UTC

GitHub Revision: e649bd3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	1.157m	15.314ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.040s	57.363us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.360s	94.550us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	16.610s	11.143ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	15.560s	644.839us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	1.590s	28.608us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.360s	94.550us	1	1	100.00
		spi_device_csr_aliasing	15.560s	644.839us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.840s	20.982us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.210s	141.031us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	0.820s	15.936us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	0.740s	1.164us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	0.790s	8.632us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	0.930s	13.299us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	0.930s	13.299us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	5.070s	1.488ms	1	1	100.00
		spi_device_tpm_sts_read	1.030s	92.923us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	15.510s	5.445ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	9.140s	17.911ms	1	1	100.00
		spi_device_flash_all	2.716m	167.690ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	7.200s	12.305ms	1	1	100.00
		spi_device_flash_all	2.716m	167.690ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	7.200s	12.305ms	1	1	100.00
		spi_device_flash_all	2.716m	167.690ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	2.716m	167.690ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	5.350s	550.578us	1	1	100.00
		spi_device_flash_all	2.716m	167.690ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	5.350s	550.578us	1	1	100.00
		spi_device_flash_all	2.716m	167.690ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	5.350s	550.578us	1	1	100.00
		spi_device_flash_all	2.716m	167.690ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	5.350s	550.578us	1	1	100.00
		spi_device_flash_all	2.716m	167.690ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	5.350s	550.578us	1	1	100.00
		spi_device_flash_all	2.716m	167.690ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	3.450s	467.607us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	9.350s	13.282ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	9.350s	13.282ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	9.350s	13.282ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	8.590s	1.601ms	1	1	100.00
		spi_device_read_buffer_direct	5.930s	1.845ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	9.350s	13.282ms	1	1	100.00
		spi_device_flash_all	2.716m	167.690ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	2.716m	167.690ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	2.716m	167.690ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	10.020s	1.482ms	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	10.020s	1.482ms	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	1.157m	15.314ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	2.541m	18.447ms	1	1	100.00
V2	stress_all	spi_device_stress_all	1.320s	96.339us	1	1	100.00
V2	alert_test	spi_device_alert_test	0.820s	17.372us	1	1	100.00
V2	intr_test	spi_device_intr_test	0.780s	100.106us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	3.280s	132.974us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	3.280s	132.974us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.040s	57.363us	1	1	100.00
		spi_device_csr_rw	1.360s	94.550us	1	1	100.00
		spi_device_csr_aliasing	15.560s	644.839us	1	1	100.00
		spi_device_same_csr_outstanding	1.460s	26.548us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.040s	57.363us	1	1	100.00
		spi_device_csr_rw	1.360s	94.550us	1	1	100.00
		spi_device_csr_aliasing	15.560s	644.839us	1	1	100.00
		spi_device_same_csr_outstanding	1.460s	26.548us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.320s	118.708us	1	1	100.00
		spi_device_tl_intg_err	9.290s	214.898us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	9.290s	214.898us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	14.920s	2.888ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.56468972469434982039238898508784491894778765414335917063480076378591711854678
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @    978563 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[20])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @    978563 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @    978563 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[916])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.45285022596931701246418181080962817738751194991996459239662156460281063782169
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   6087420 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xde1c50 [110111100001110001010000] vs 0x0 [0])
        UVM_ERROR @   6143420 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x373491 [1101110011010010010001] vs 0x0 [0])
        UVM_ERROR @   6194420 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x872ab9 [100001110010101010111001] vs 0x0 [0])
        UVM_ERROR @   6259420 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xf5bfd3 [111101011011111111010011] vs 0x0 [0])
        UVM_ERROR @   6326420 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x23368d [1000110011011010001101] vs 0x0 [0])