| V1 |
smoke |
spi_device_flash_and_tpm |
1.829m |
44.728ms |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
spi_device_csr_hw_reset |
0.970s |
19.397us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
spi_device_csr_rw |
1.180s |
27.340us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
spi_device_csr_bit_bash |
8.550s |
3.002ms |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
spi_device_csr_aliasing |
5.430s |
473.110us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
spi_device_csr_mem_rw_with_rand_reset |
1.320s |
56.053us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
spi_device_csr_rw |
1.180s |
27.340us |
1 |
1 |
100.00 |
|
|
spi_device_csr_aliasing |
5.430s |
473.110us |
1 |
1 |
100.00 |
| V1 |
mem_walk |
spi_device_mem_walk |
0.740s |
30.632us |
1 |
1 |
100.00 |
| V1 |
mem_partial_access |
spi_device_mem_partial_access |
1.770s |
113.484us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
8 |
8 |
100.00 |
| V2 |
csb_read |
spi_device_csb_read |
0.840s |
52.152us |
1 |
1 |
100.00 |
| V2 |
mem_parity |
spi_device_mem_parity |
1.050s |
32.003us |
1 |
1 |
100.00 |
| V2 |
mem_cfg |
spi_device_ram_cfg |
0.730s |
32.941us |
1 |
1 |
100.00 |
| V2 |
tpm_read |
spi_device_tpm_rw |
1.060s |
14.480us |
1 |
1 |
100.00 |
| V2 |
tpm_write |
spi_device_tpm_rw |
1.060s |
14.480us |
1 |
1 |
100.00 |
| V2 |
tpm_hw_reg |
spi_device_tpm_read_hw_reg |
1.160s |
71.158us |
1 |
1 |
100.00 |
|
|
spi_device_tpm_sts_read |
0.850s |
121.486us |
1 |
1 |
100.00 |
| V2 |
tpm_fully_random_case |
spi_device_tpm_all |
5.790s |
2.140ms |
1 |
1 |
100.00 |
| V2 |
pass_cmd_filtering |
spi_device_pass_cmd_filtering |
6.970s |
2.182ms |
1 |
1 |
100.00 |
|
|
spi_device_flash_all |
22.550s |
10.354ms |
1 |
1 |
100.00 |
| V2 |
pass_addr_translation |
spi_device_pass_addr_payload_swap |
3.780s |
396.724us |
1 |
1 |
100.00 |
|
|
spi_device_flash_all |
22.550s |
10.354ms |
1 |
1 |
100.00 |
| V2 |
pass_payload_translation |
spi_device_pass_addr_payload_swap |
3.780s |
396.724us |
1 |
1 |
100.00 |
|
|
spi_device_flash_all |
22.550s |
10.354ms |
1 |
1 |
100.00 |
| V2 |
cmd_info_slots |
spi_device_flash_all |
22.550s |
10.354ms |
1 |
1 |
100.00 |
| V2 |
cmd_read_status |
spi_device_intercept |
5.900s |
1.228ms |
1 |
1 |
100.00 |
|
|
spi_device_flash_all |
22.550s |
10.354ms |
1 |
1 |
100.00 |
| V2 |
cmd_read_jedec |
spi_device_intercept |
5.900s |
1.228ms |
1 |
1 |
100.00 |
|
|
spi_device_flash_all |
22.550s |
10.354ms |
1 |
1 |
100.00 |
| V2 |
cmd_read_sfdp |
spi_device_intercept |
5.900s |
1.228ms |
1 |
1 |
100.00 |
|
|
spi_device_flash_all |
22.550s |
10.354ms |
1 |
1 |
100.00 |
| V2 |
cmd_fast_read |
spi_device_intercept |
5.900s |
1.228ms |
1 |
1 |
100.00 |
|
|
spi_device_flash_all |
22.550s |
10.354ms |
1 |
1 |
100.00 |
| V2 |
cmd_read_pipeline |
spi_device_intercept |
5.900s |
1.228ms |
1 |
1 |
100.00 |
|
|
spi_device_flash_all |
22.550s |
10.354ms |
1 |
1 |
100.00 |
| V2 |
flash_cmd_upload |
spi_device_upload |
3.940s |
1.668ms |
1 |
1 |
100.00 |
| V2 |
mailbox_command |
spi_device_mailbox |
10.320s |
1.359ms |
1 |
1 |
100.00 |
| V2 |
mailbox_cross_outside_command |
spi_device_mailbox |
10.320s |
1.359ms |
1 |
1 |
100.00 |
| V2 |
mailbox_cross_inside_command |
spi_device_mailbox |
10.320s |
1.359ms |
1 |
1 |
100.00 |
| V2 |
cmd_read_buffer |
spi_device_flash_mode |
45.790s |
3.870ms |
1 |
1 |
100.00 |
|
|
spi_device_read_buffer_direct |
3.450s |
190.502us |
1 |
1 |
100.00 |
| V2 |
cmd_dummy_cycle |
spi_device_mailbox |
10.320s |
1.359ms |
1 |
1 |
100.00 |
|
|
spi_device_flash_all |
22.550s |
10.354ms |
1 |
1 |
100.00 |
| V2 |
quad_spi |
spi_device_flash_all |
22.550s |
10.354ms |
1 |
1 |
100.00 |
| V2 |
dual_spi |
spi_device_flash_all |
22.550s |
10.354ms |
1 |
1 |
100.00 |
| V2 |
4b_3b_feature |
spi_device_cfg_cmd |
5.500s |
1.114ms |
1 |
1 |
100.00 |
| V2 |
write_enable_disable |
spi_device_cfg_cmd |
5.500s |
1.114ms |
1 |
1 |
100.00 |
| V2 |
TPM_with_flash_or_passthrough_mode |
spi_device_flash_and_tpm |
1.829m |
44.728ms |
1 |
1 |
100.00 |
| V2 |
tpm_and_flash_trans_with_min_inactive_time |
spi_device_flash_and_tpm_min_idle |
51.030s |
29.822ms |
1 |
1 |
100.00 |
| V2 |
stress_all |
spi_device_stress_all |
5.106m |
51.442ms |
1 |
1 |
100.00 |
| V2 |
alert_test |
spi_device_alert_test |
0.880s |
25.876us |
1 |
1 |
100.00 |
| V2 |
intr_test |
spi_device_intr_test |
0.640s |
37.387us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
spi_device_tl_errors |
1.690s |
34.231us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
spi_device_tl_errors |
1.690s |
34.231us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
spi_device_csr_hw_reset |
0.970s |
19.397us |
1 |
1 |
100.00 |
|
|
spi_device_csr_rw |
1.180s |
27.340us |
1 |
1 |
100.00 |
|
|
spi_device_csr_aliasing |
5.430s |
473.110us |
1 |
1 |
100.00 |
|
|
spi_device_same_csr_outstanding |
1.800s |
28.951us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
spi_device_csr_hw_reset |
0.970s |
19.397us |
1 |
1 |
100.00 |
|
|
spi_device_csr_rw |
1.180s |
27.340us |
1 |
1 |
100.00 |
|
|
spi_device_csr_aliasing |
5.430s |
473.110us |
1 |
1 |
100.00 |
|
|
spi_device_same_csr_outstanding |
1.800s |
28.951us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
22 |
22 |
100.00 |
| V2S |
tl_intg_err |
spi_device_sec_cm |
1.090s |
41.820us |
1 |
1 |
100.00 |
|
|
spi_device_tl_intg_err |
10.970s |
731.332us |
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
spi_device_tl_intg_err |
10.970s |
731.332us |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
2 |
2 |
100.00 |
|
Unmapped tests |
spi_device_flash_mode_ignore_cmds |
1.460m |
18.230ms |
1 |
1 |
100.00 |
|
|
TOTAL |
|
|
33 |
33 |
100.00 |