SPI_HOST Simulation Results

Thursday September 04 2025 19:17:11 UTC

GitHub Revision: e649bd3

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	14.000s	216.716us	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	3.000s	47.949us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	3.000s	39.612us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	3.000s	169.177us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	2.000s	29.198us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	3.000s	97.260us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	3.000s	39.612us	1	1	100.00
		spi_host_csr_aliasing	2.000s	29.198us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	3.000s	36.604us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	2.000s	43.190us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	11.000s	23.205us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	10.000s	58.762us	1	1	100.00
		spi_host_error_cmd	9.000s	37.232us	1	1	100.00
		spi_host_event	2.467m	144.223ms	1	1	100.00
V2	clock_rate	spi_host_speed	13.000s	205.979us	1	1	100.00
V2	speed	spi_host_speed	13.000s	205.979us	1	1	100.00
V2	chip_select_timing	spi_host_speed	13.000s	205.979us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	11.000s	92.823us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	3.000s	116.408us	1	1	100.00
V2	cpol_cpha	spi_host_speed	13.000s	205.979us	1	1	100.00
V2	full_cycle	spi_host_speed	13.000s	205.979us	1	1	100.00
V2	duplex	spi_host_smoke	14.000s	216.716us	1	1	100.00
V2	tx_rx_only	spi_host_smoke	14.000s	216.716us	1	1	100.00
V2	stress_all	spi_host_stress_all	8.000s	748.835us	1	1	100.00
V2	spien	spi_host_spien	18.000s	4.543ms	1	1	100.00
V2	stall	spi_host_status_stall	22.000s	1.617ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	3.000s	348.788us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	10.000s	58.762us	1	1	100.00
V2	alert_test	spi_host_alert_test	2.000s	37.702us	1	1	100.00
V2	intr_test	spi_host_intr_test	3.000s	16.202us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	4.000s	129.325us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	4.000s	129.325us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	3.000s	47.949us	1	1	100.00
		spi_host_csr_rw	3.000s	39.612us	1	1	100.00
		spi_host_csr_aliasing	2.000s	29.198us	1	1	100.00
		spi_host_same_csr_outstanding	3.000s	40.606us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	3.000s	47.949us	1	1	100.00
		spi_host_csr_rw	3.000s	39.612us	1	1	100.00
		spi_host_csr_aliasing	2.000s	29.198us	1	1	100.00
		spi_host_same_csr_outstanding	3.000s	40.606us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	3.000s	295.512us	1	1	100.00
		spi_host_sec_cm	3.000s	169.545us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	3.000s	295.512us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	2.083m	5.803ms	1	1	100.00
		TOTAL			26	26	100.00