SRAM_CTRL/MAIN Simulation Results

Thursday September 04 2025 19:17:11 UTC

GitHub Revision: e649bd3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	9.970s	854.580us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.810s	39.805us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.780s	11.780us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.860s	468.575us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.010s	13.848us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.730s	348.821us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.780s	11.780us	1	1	100.00
		sram_ctrl_csr_aliasing	1.010s	13.848us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	3.533m	21.008ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	46.940s	2.222ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	3.216m	5.346ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.577m	9.926ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	27.927m	387.005ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	5.588m	8.232ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	40.000s	9.535ms	1	1	100.00
V2	executable	sram_ctrl_executable	35.610s	17.308ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	8.140s	2.732ms	1	1	100.00
		sram_ctrl_partial_access_b2b	4.827m	13.609ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	7.120s	690.831us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	6.880s	695.153us	1	1	100.00
		sram_ctrl_throughput_w_readback	16.070s	3.060ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	11.895m	4.573ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	2.580s	3.343ms	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	18.341m	617.720ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.880s	104.412us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.740s	67.056us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.740s	67.056us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.810s	39.805us	1	1	100.00
		sram_ctrl_csr_rw	0.780s	11.780us	1	1	100.00
		sram_ctrl_csr_aliasing	1.010s	13.848us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.060s	46.441us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.810s	39.805us	1	1	100.00
		sram_ctrl_csr_rw	0.780s	11.780us	1	1	100.00
		sram_ctrl_csr_aliasing	1.010s	13.848us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.060s	46.441us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	16.170s	6.844ms	0	1	0.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.810s	5.065us	0	1	0.00
		sram_ctrl_tl_intg_err	1.460s	777.344us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.810s	5.065us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.460s	777.344us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	11.895m	4.573ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	11.895m	4.573ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.780s	11.780us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	35.610s	17.308ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	35.610s	17.308ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	35.610s	17.308ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	40.000s	9.535ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	8.150s	1.376ms	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	16.170s	6.844ms	0	1	0.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	6.040s	3.896ms	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	9.970s	854.580us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	9.970s	854.580us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	35.610s	17.308ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.810s	5.065us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	40.000s	9.535ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.810s	5.065us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.810s	5.065us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	9.970s	854.580us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.810s	5.065us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	23.910s	3.323ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• Offending '(!$isunknown(rdata_o))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.49402613395099566375067710002403633239806691813509448948733169038549764523813
      Line 99, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   5065431 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   5065431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:

  • Test sram_ctrl_passthru_mem_tl_intg_err has 1 failures.

    • 0.sram_ctrl_passthru_mem_tl_intg_err.113982035239906420938758594714989663514061673000136428457654182406828733111756
      Line 123, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_passthru_mem_tl_intg_err/latest/run.log

        UVM_ERROR @ 6843548892 ps: uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer [uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer] get_next_item/try_next_item called twice without item_done or get in between
        UVM_INFO @ 6843548892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---